mirror of https://github.com/xemu-project/xemu.git
hw/pci-host/bonito: Move away from old_mmio accessors
Move away from the old_mmio MemoryRegion accessors in the bonito pci controller. This device is used only in the MIPS "fulong2e" machine. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180802155147.1863-3-peter.maydell@linaro.org Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
This commit is contained in:
Peter Maydell
Gerd Hoffmann
parent
5f92799877
commit
421ab72567
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@ -460,8 +460,8 @@ static uint32_t bonito_sbridge_pciaddr(void *opaque, hwaddr addr)
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return pciaddr;
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}
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static void bonito_spciconf_writeb(void *opaque, hwaddr addr,
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uint32_t val)
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static void bonito_spciconf_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned size)
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{
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PCIBonitoState *s = opaque;
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PCIDevice *d = PCI_DEVICE(s);
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@ -469,34 +469,8 @@ static void bonito_spciconf_writeb(void *opaque, hwaddr addr,
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uint32_t pciaddr;
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uint16_t status;
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DPRINTF("bonito_spciconf_writeb "TARGET_FMT_plx" val %x\n", addr, val);
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pciaddr = bonito_sbridge_pciaddr(s, addr);
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if (pciaddr == 0xffffffff) {
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return;
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}
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/* set the pci address in s->config_reg */
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phb->config_reg = (pciaddr) | (1u << 31);
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pci_data_write(phb->bus, phb->config_reg, val & 0xff, 1);
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/* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
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status = pci_get_word(d->config + PCI_STATUS);
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status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
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pci_set_word(d->config + PCI_STATUS, status);
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}
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static void bonito_spciconf_writew(void *opaque, hwaddr addr,
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uint32_t val)
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{
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PCIBonitoState *s = opaque;
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PCIDevice *d = PCI_DEVICE(s);
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PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
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uint32_t pciaddr;
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uint16_t status;
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DPRINTF("bonito_spciconf_writew "TARGET_FMT_plx" val %x\n", addr, val);
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assert((addr & 0x1) == 0);
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DPRINTF("bonito_spciconf_write "TARGET_FMT_plx" size %d val %x\n",
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addr, size, val);
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pciaddr = bonito_sbridge_pciaddr(s, addr);
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@ -506,7 +480,7 @@ static void bonito_spciconf_writew(void *opaque, hwaddr addr,
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/* set the pci address in s->config_reg */
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phb->config_reg = (pciaddr) | (1u << 31);
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pci_data_write(phb->bus, phb->config_reg, val, 2);
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pci_data_write(phb->bus, phb->config_reg, val, size);
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/* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
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status = pci_get_word(d->config + PCI_STATUS);
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@ -514,8 +488,7 @@ static void bonito_spciconf_writew(void *opaque, hwaddr addr,
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pci_set_word(d->config + PCI_STATUS, status);
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}
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static void bonito_spciconf_writel(void *opaque, hwaddr addr,
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uint32_t val)
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static uint64_t bonito_spciconf_read(void *opaque, hwaddr addr, unsigned size)
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{
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PCIBonitoState *s = opaque;
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PCIDevice *d = PCI_DEVICE(s);
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@ -523,38 +496,12 @@ static void bonito_spciconf_writel(void *opaque, hwaddr addr,
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uint32_t pciaddr;
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uint16_t status;
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DPRINTF("bonito_spciconf_writel "TARGET_FMT_plx" val %x\n", addr, val);
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assert((addr & 0x3) == 0);
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DPRINTF("bonito_spciconf_read "TARGET_FMT_plx" size %d\n", addr, size);
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pciaddr = bonito_sbridge_pciaddr(s, addr);
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if (pciaddr == 0xffffffff) {
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return;
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}
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/* set the pci address in s->config_reg */
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phb->config_reg = (pciaddr) | (1u << 31);
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pci_data_write(phb->bus, phb->config_reg, val, 4);
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/* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
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status = pci_get_word(d->config + PCI_STATUS);
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status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
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pci_set_word(d->config + PCI_STATUS, status);
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}
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static uint32_t bonito_spciconf_readb(void *opaque, hwaddr addr)
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{
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PCIBonitoState *s = opaque;
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PCIDevice *d = PCI_DEVICE(s);
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PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
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uint32_t pciaddr;
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uint16_t status;
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DPRINTF("bonito_spciconf_readb "TARGET_FMT_plx"\n", addr);
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pciaddr = bonito_sbridge_pciaddr(s, addr);
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if (pciaddr == 0xffffffff) {
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return 0xff;
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return MAKE_64BIT_MASK(0, size * 8);
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}
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/* set the pci address in s->config_reg */
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@ -565,79 +512,17 @@ static uint32_t bonito_spciconf_readb(void *opaque, hwaddr addr)
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status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
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pci_set_word(d->config + PCI_STATUS, status);
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return pci_data_read(phb->bus, phb->config_reg, 1);
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}
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static uint32_t bonito_spciconf_readw(void *opaque, hwaddr addr)
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{
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PCIBonitoState *s = opaque;
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PCIDevice *d = PCI_DEVICE(s);
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PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
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uint32_t pciaddr;
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uint16_t status;
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DPRINTF("bonito_spciconf_readw "TARGET_FMT_plx"\n", addr);
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assert((addr & 0x1) == 0);
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pciaddr = bonito_sbridge_pciaddr(s, addr);
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if (pciaddr == 0xffffffff) {
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return 0xffff;
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}
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/* set the pci address in s->config_reg */
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phb->config_reg = (pciaddr) | (1u << 31);
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/* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
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status = pci_get_word(d->config + PCI_STATUS);
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status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
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pci_set_word(d->config + PCI_STATUS, status);
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return pci_data_read(phb->bus, phb->config_reg, 2);
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}
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static uint32_t bonito_spciconf_readl(void *opaque, hwaddr addr)
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{
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PCIBonitoState *s = opaque;
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PCIDevice *d = PCI_DEVICE(s);
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PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
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uint32_t pciaddr;
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uint16_t status;
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DPRINTF("bonito_spciconf_readl "TARGET_FMT_plx"\n", addr);
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assert((addr & 0x3) == 0);
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pciaddr = bonito_sbridge_pciaddr(s, addr);
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if (pciaddr == 0xffffffff) {
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return 0xffffffff;
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}
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/* set the pci address in s->config_reg */
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phb->config_reg = (pciaddr) | (1u << 31);
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/* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
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status = pci_get_word(d->config + PCI_STATUS);
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status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
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pci_set_word(d->config + PCI_STATUS, status);
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return pci_data_read(phb->bus, phb->config_reg, 4);
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return pci_data_read(phb->bus, phb->config_reg, size);
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}
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/* south bridge PCI configure space. 0x1fe8 0000 - 0x1fef ffff */
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static const MemoryRegionOps bonito_spciconf_ops = {
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.old_mmio = {
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.read = {
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bonito_spciconf_readb,
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bonito_spciconf_readw,
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bonito_spciconf_readl,
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},
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.write = {
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bonito_spciconf_writeb,
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bonito_spciconf_writew,
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bonito_spciconf_writel,
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},
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},
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.read = bonito_spciconf_read,
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.write = bonito_spciconf_write,
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.valid.min_access_size = 1,
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.valid.max_access_size = 4,
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.impl.min_access_size = 1,
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.impl.max_access_size = 4,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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