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hw/intc: Make zeroth priority register read-only 

According to PLIC specification chapter 4, zeroth
priority register is reserved. Discard writes to
this register.

Signed-off-by: Sergey Makarov <s.makarov@syntacore.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240918140229.124329-2-s.makarov@syntacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Sergey Makarov 2024-09-18 17:02:28 +03:00 committed by Alistair Francis
parent bfd12c92cc
commit 41fc1f0294
1 changed files with 7 additions and 2 deletions
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9
hw/intc/sifive_plic.c
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@ -189,8 +189,13 @@ static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value,
if (addr_between(addr, plic->priority_base, plic->num_sources << 2)) {
uint32_t irq = (addr - plic->priority_base) >> 2;
if (((plic->num_priorities + 1) & plic->num_priorities) == 0) {
if (irq == 0) {
/* IRQ 0 source prioority is reserved */
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Invalid source priority write 0x%"
HWADDR_PRIx "\n", __func__, addr);
return;
} else if (((plic->num_priorities + 1) & plic->num_priorities) == 0) {
/*
* if "num_priorities + 1" is power-of-2, make each register bit of
* interrupt priority WARL (Write-Any-Read-Legal). Just filter