mirror of https://github.com/xemu-project/xemu.git
hw/intc: Make zeroth priority register read-only
According to PLIC specification chapter 4, zeroth priority register is reserved. Discard writes to this register. Signed-off-by: Sergey Makarov <s.makarov@syntacore.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240918140229.124329-2-s.makarov@syntacore.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -189,8 +189,13 @@ static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value,
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if (addr_between(addr, plic->priority_base, plic->num_sources << 2)) {
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uint32_t irq = (addr - plic->priority_base) >> 2;
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if (((plic->num_priorities + 1) & plic->num_priorities) == 0) {
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if (irq == 0) {
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/* IRQ 0 source prioority is reserved */
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Invalid source priority write 0x%"
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HWADDR_PRIx "\n", __func__, addr);
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return;
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} else if (((plic->num_priorities + 1) & plic->num_priorities) == 0) {
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/*
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* if "num_priorities + 1" is power-of-2, make each register bit of
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* interrupt priority WARL (Write-Any-Read-Legal). Just filter
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