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accel/tcg: Trigger watchpoints from atomic_mmu_lookup 

Fixes a bug in that we weren't reporting these changes.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-02-22 22:41:01 -10:00
parent 019a98083a
commit 417aeaff54
1 changed files with 29 additions and 11 deletions
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34
accel/tcg/cputlb.c
View File

@ -1767,6 +1767,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
CPUTLBEntry *tlbe; CPUTLBEntry *tlbe;
target_ulong tlb_addr; target_ulong tlb_addr;
void *hostaddr; void *hostaddr;
CPUTLBEntryFull *full;
tcg_debug_assert(mmu_idx < NB_MMU_MODES); tcg_debug_assert(mmu_idx < NB_MMU_MODES);
@ -1805,18 +1806,27 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
tlb_addr = tlb_addr_write(tlbe) & ~TLB_INVALID_MASK; tlb_addr = tlb_addr_write(tlbe) & ~TLB_INVALID_MASK;
} }
/* Let the guest notice RMW on a write-only page. */ if (prot & PAGE_READ) {
if ((prot & PAGE_READ) && /*
unlikely(tlbe->addr_read != (tlb_addr & ~TLB_NOTDIRTY))) { * Let the guest notice RMW on a write-only page.
* We have just verified that the page is writable.
* Subpage lookups may have left TLB_INVALID_MASK set,
* but addr_read will only be -1 if PAGE_READ was unset.
*/
if (unlikely(tlbe->addr_read == -1)) {
tlb_fill(env_cpu(env), addr, size, tlb_fill(env_cpu(env), addr, size,
MMU_DATA_LOAD, mmu_idx, retaddr); MMU_DATA_LOAD, mmu_idx, retaddr);
/* /*
* Since we don't support reads and writes to different addresses, * Since we don't support reads and writes to different
* and we do have the proper page loaded for write, this shouldn't * addresses, and we do have the proper page loaded for
* ever return. But just in case, handle via stop-the-world. * write, this shouldn't ever return. But just in case,
* handle via stop-the-world.
*/ */
goto stop_the_world; goto stop_the_world;
} }
/* Collect TLB_WATCHPOINT for read. */
tlb_addr |= tlbe->addr_read;
}
} else /* if (prot & PAGE_READ) */ { } else /* if (prot & PAGE_READ) */ {
tlb_addr = tlbe->addr_read; tlb_addr = tlbe->addr_read;
if (!tlb_hit(tlb_addr, addr)) { if (!tlb_hit(tlb_addr, addr)) {
@ -1838,10 +1848,18 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
} }
hostaddr = (void *)((uintptr_t)addr + tlbe->addend); hostaddr = (void *)((uintptr_t)addr + tlbe->addend);
full = &env_tlb(env)->d[mmu_idx].fulltlb[index];
if (unlikely(tlb_addr & TLB_NOTDIRTY)) { if (unlikely(tlb_addr & TLB_NOTDIRTY)) {
notdirty_write(env_cpu(env), addr, size, notdirty_write(env_cpu(env), addr, size, full, retaddr);
&env_tlb(env)->d[mmu_idx].fulltlb[index], retaddr); }
if (unlikely(tlb_addr & TLB_WATCHPOINT)) {
QEMU_BUILD_BUG_ON(PAGE_READ != BP_MEM_READ);
QEMU_BUILD_BUG_ON(PAGE_WRITE != BP_MEM_WRITE);
/* therefore prot == watchpoint bits */
cpu_check_watchpoint(env_cpu(env), addr, size,
full->attrs, prot, retaddr);
} }
return hostaddr; return hostaddr;