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target/xtensa: FLIX support, various fixes and test improvements 

- add FLIX (flexible length instructions extension) support;
 - make testsuite runnable on wider range of xtensa cores;
 - add floating point opcode tests;
 - don't add duplicate 'static' in import_core.sh script;
 - fix undefined opcodes detection in test_mmuhifi_c3 overlay.
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Merge remote-tracking branch 'remotes/xtensa/tags/20190228-xtensa' into staging

target/xtensa: FLIX support, various fixes and test improvements

- add FLIX (flexible length instructions extension) support;
- make testsuite runnable on wider range of xtensa cores;
- add floating point opcode tests;
- don't add duplicate 'static' in import_core.sh script;
- fix undefined opcodes detection in test_mmuhifi_c3 overlay.

# gpg: Signature made Thu 28 Feb 2019 12:53:23 GMT
# gpg:                using RSA key 2B67854B98E5327DCDEB17D851F9CC91F83FA044
# gpg:                issuer "jcmvbkbc@gmail.com"
# gpg: Good signature from "Max Filippov <filippov@cadence.com>" [unknown]
# gpg:                 aka "Max Filippov <max.filippov@cogentembedded.com>" [full]
# gpg:                 aka "Max Filippov <jcmvbkbc@gmail.com>" [full]
# Primary key fingerprint: 2B67 854B 98E5 327D CDEB  17D8 51F9 CC91 F83F A044

* remotes/xtensa/tags/20190228-xtensa: (40 commits)
  tests/tcg/xtensa: add FPU2000 coprocessor tests
  tests/tcg/xtensa: add FP1 group tests
  tests/tcg/xtensa: add FP0 group conversion tests
  tests/tcg/xtensa: add FP0 group arithmetic tests
  tests/tcg/xtensa: add LSCI/LSCX group tests
  tests/tcg/xtensa: add test for FLIX
  tests/tcg/xtensa: conditionalize MMU-related tests
  tests/tcg/xtensa: conditionalize windowed register tests
  tests/tcg/xtensa: conditionalize and fix s32c1i tests
  tests/tcg/xtensa: fix SR tests for big endian configs
  tests/tcg/xtensa: conditionalize and expand SR tests
  tests/tcg/xtensa: conditionalize timer/CCOUNT tests
  tests/tcg/xtensa: conditionalize interrupt tests
  tests/tcg/xtensa: add straightforward conditionals
  tests/tcg/xtensa: conditionalize cache option tests
  tests/tcg/xtensa: conditionalize debug option tests
  tests/tcg/xtensa: enable boolean tests
  tests/tcg/xtensa: fix endianness issues in test_b
  tests/tcg/xtensa: don't use optional opcodes in generic code
  tests/tcg/xtensa: support configs with LITBASE
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2019-02-28 19:04:16 +00:00
parent 9403bccfe3 de0cebd930
commit 4179575898
41 changed files with 3257 additions and 1843 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1322
target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c
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File diff suppressed because it is too large Load Diff

40
target/xtensa/cpu.h
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@ -131,6 +131,7 @@ enum {
ACCLO = 16,
ACCHI = 17,
MR = 32,
PREFCTL = 40,
WINDOW_BASE = 72,
WINDOW_START = 73,
PTEVADDR = 83,
@ -345,14 +346,21 @@ typedef struct XtensaMemory {
} location[MAX_NMEMORY];
} XtensaMemory;
typedef struct opcode_arg {
uint32_t imm;
uint32_t raw_imm;
void *in;
void *out;
} OpcodeArg;
typedef struct DisasContext DisasContext;
typedef void (*XtensaOpcodeOp)(DisasContext *dc, const uint32_t arg[],
typedef void (*XtensaOpcodeOp)(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[]);
typedef bool (*XtensaOpcodeBoolTest)(DisasContext *dc,
const uint32_t arg[],
const OpcodeArg arg[],
const uint32_t par[]);
typedef uint32_t (*XtensaOpcodeUintTest)(DisasContext *dc,
const uint32_t arg[],
const OpcodeArg arg[],
const uint32_t par[]);
enum {
@ -368,19 +376,34 @@ enum {
XTENSA_OP_DIVIDE_BY_ZERO = 0x100,
/* Postprocessing flags */
XTENSA_OP_CHECK_INTERRUPTS = 0x200,
XTENSA_OP_EXIT_TB_M1 = 0x400,
XTENSA_OP_EXIT_TB_0 = 0x800,
XTENSA_OP_SYNC_REGISTER_WINDOW = 0x1000,
XTENSA_OP_POSTPROCESS =
XTENSA_OP_CHECK_INTERRUPTS |
XTENSA_OP_EXIT_TB_M1 |
XTENSA_OP_EXIT_TB_0 |
XTENSA_OP_SYNC_REGISTER_WINDOW,
XTENSA_OP_NAME_ARRAY = 0x8000,
XTENSA_OP_CONTROL_FLOW = 0x10000,
XTENSA_OP_STORE = 0x20000,
XTENSA_OP_LOAD = 0x40000,
XTENSA_OP_LOAD_STORE =
XTENSA_OP_LOAD | XTENSA_OP_STORE,
};
typedef struct XtensaOpcodeOps {
const char *name;
const void *name;
XtensaOpcodeOp translate;
XtensaOpcodeBoolTest test_ill;
XtensaOpcodeUintTest test_overflow;
const uint32_t *par;
uint32_t op_flags;
uint32_t windowed_register_op;
uint32_t coprocessor;
} XtensaOpcodeOps;
@ -438,6 +461,8 @@ struct XtensaConfig {
xtensa_isa isa;
XtensaOpcodeOps **opcode_ops;
const XtensaOpcodeTranslators **opcode_translators;
xtensa_regfile a_regfile;
void ***regfile;
uint32_t clock_freq_khz;
@ -474,6 +499,7 @@ typedef struct CPUXtensaState {
float64 f64;
} fregs[16];
float_status fp_status;
uint32_t windowbase_next;
#ifndef CONFIG_USER_ONLY
xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE];
@ -565,8 +591,8 @@ void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
XTENSA_CPU_TYPE_NAME(XTENSA_DEFAULT_CPU_NOMMU_MODEL)
void xtensa_translate_init(void);
void **xtensa_get_regfile_by_name(const char *name);
void xtensa_breakpoint_handler(CPUState *cs);
void xtensa_finalize_config(XtensaConfig *config);
void xtensa_register_core(XtensaConfigList *node);
void xtensa_sim_open_console(Chardev *chr);
void check_interrupts(CPUXtensaState *s);
@ -588,8 +614,6 @@ static inline void xtensa_select_static_vectors(CPUXtensaState *env,
env->static_vectors = n;
}
void xtensa_runstall(CPUXtensaState *env, bool runstall);
XtensaOpcodeOps *xtensa_find_opcode_ops(const XtensaOpcodeTranslators *t,
const char *opcode);
#define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt))
#define XTENSA_OPTION_ALL (~(uint64_t)0)

94
target/xtensa/helper.c
View File

@ -30,24 +30,60 @@
#include "exec/exec-all.h"
#include "exec/gdbstub.h"
#include "exec/helper-proto.h"
#include "qemu/error-report.h"
#include "qemu/host-utils.h"
static struct XtensaConfigList *xtensa_cores;
static void xtensa_core_class_init(ObjectClass *oc, void *data)
static void add_translator_to_hash(GHashTable *translator,
const char *name,
const XtensaOpcodeOps *opcode)
{
CPUClass *cc = CPU_CLASS(oc);
XtensaCPUClass *xcc = XTENSA_CPU_CLASS(oc);
const XtensaConfig *config = data;
if (!g_hash_table_insert(translator, (void *)name, (void *)opcode)) {
error_report("Multiple definitions of '%s' opcode in a single table",
name);
}
}
xcc->config = config;
static GHashTable *hash_opcode_translators(const XtensaOpcodeTranslators *t)
{
unsigned i, j;
GHashTable *translator = g_hash_table_new(g_str_hash, g_str_equal);
/* Use num_core_regs to see only non-privileged registers in an unmodified
* gdb. Use num_regs to see all registers. gdb modification is required
* for that: reset bit 0 in the 'flags' field of the registers definitions
* in the gdb/xtensa-config.c inside gdb source tree or inside gdb overlay.
*/
cc->gdb_num_core_regs = config->gdb_regmap.num_regs;
for (i = 0; i < t->num_opcodes; ++i) {
if (t->opcode[i].op_flags & XTENSA_OP_NAME_ARRAY) {
const char * const *name = t->opcode[i].name;
for (j = 0; name[j]; ++j) {
add_translator_to_hash(translator,
(void *)name[j],
(void *)(t->opcode + i));
}
} else {
add_translator_to_hash(translator,
(void *)t->opcode[i].name,
(void *)(t->opcode + i));
}
}
return translator;
}
static XtensaOpcodeOps *
xtensa_find_opcode_ops(const XtensaOpcodeTranslators *t,
const char *name)
{
static GHashTable *translators;
GHashTable *translator;
if (translators == NULL) {
translators = g_hash_table_new(g_direct_hash, g_direct_equal);
}
translator = g_hash_table_lookup(translators, t);
if (translator == NULL) {
translator = hash_opcode_translators(t);
g_hash_table_insert(translators, (void *)t, translator);
}
return g_hash_table_lookup(translator, name);
}
static void init_libisa(XtensaConfig *config)
@ -55,11 +91,13 @@ static void init_libisa(XtensaConfig *config)
unsigned i, j;
unsigned opcodes;
unsigned formats;
unsigned regfiles;
config->isa = xtensa_isa_init(config->isa_internal, NULL, NULL);
assert(xtensa_isa_maxlength(config->isa) <= MAX_INSN_LENGTH);
opcodes = xtensa_isa_num_opcodes(config->isa);
formats = xtensa_isa_num_formats(config->isa);
regfiles = xtensa_isa_num_regfiles(config->isa);
config->opcode_ops = g_new(XtensaOpcodeOps *, opcodes);
for (i = 0; i < formats; ++i) {
@ -88,9 +126,23 @@ static void init_libisa(XtensaConfig *config)
#endif
config->opcode_ops[i] = ops;
}
config->a_regfile = xtensa_regfile_lookup(config->isa, "AR");
config->regfile = g_new(void **, regfiles);
for (i = 0; i < regfiles; ++i) {
const char *name = xtensa_regfile_name(config->isa, i);
config->regfile[i] = xtensa_get_regfile_by_name(name);
#ifdef DEBUG
if (config->regfile[i] == NULL) {
fprintf(stderr, "regfile '%s' not found for %s\n",
name, config->name);
}
#endif
}
}
void xtensa_finalize_config(XtensaConfig *config)
static void xtensa_finalize_config(XtensaConfig *config)
{
if (config->isa_internal) {
init_libisa(config);
@ -111,6 +163,24 @@ void xtensa_finalize_config(XtensaConfig *config)
}
}
static void xtensa_core_class_init(ObjectClass *oc, void *data)
{
CPUClass *cc = CPU_CLASS(oc);
XtensaCPUClass *xcc = XTENSA_CPU_CLASS(oc);
XtensaConfig *config = data;
xtensa_finalize_config(config);
xcc->config = config;
/*
* Use num_core_regs to see only non-privileged registers in an unmodified
* gdb. Use num_regs to see all registers. gdb modification is required
* for that: reset bit 0 in the 'flags' field of the registers definitions
* in the gdb/xtensa-config.c inside gdb source tree or inside gdb overlay.
*/
cc->gdb_num_core_regs = config->gdb_regmap.num_regs;
}
void xtensa_register_core(XtensaConfigList *node)
{
TypeInfo type = {

5
target/xtensa/helper.h
View File

@ -3,12 +3,11 @@ DEF_HELPER_3(exception_cause, noreturn, env, i32, i32)
DEF_HELPER_4(exception_cause_vaddr, noreturn, env, i32, i32, i32)
DEF_HELPER_3(debug_exception, noreturn, env, i32, i32)
DEF_HELPER_2(wsr_windowbase, void, env, i32)
DEF_HELPER_1(sync_windowbase, void, env)
DEF_HELPER_4(entry, void, env, i32, i32, i32)
DEF_HELPER_2(test_ill_retw, void, env, i32)
DEF_HELPER_2(test_underflow_retw, void, env, i32)
DEF_HELPER_2(retw, i32, env, i32)
DEF_HELPER_2(rotw, void, env, i32)
DEF_HELPER_2(retw, void, env, i32)
DEF_HELPER_3(window_check, noreturn, env, i32, i32)
DEF_HELPER_1(restore_owb, void, env)
DEF_HELPER_2(movsp, void, env, i32)

2
target/xtensa/import_core.sh
View File

@ -27,7 +27,7 @@ tar -xf "$OVERLAY" -O gdb/xtensa-config.c | \
# Fix up known issues in the xtensa-modules.c
#
tar -xf "$OVERLAY" -O binutils/xtensa-modules.c | \
sed -e 's/\(xtensa_opcode_encode_fn.*\[\] =\)/static \1/' \
sed -e 's/^\(xtensa_opcode_encode_fn.*\[\] =\)/static \1/' \
-e '/^int num_bypass_groups()/,/}/d' \
-e '/^int num_bypass_group_chunks()/,/}/d' \
-e '/^uint32 \*bypass_entry(int i)/,/}/d' \

1
target/xtensa/overlay_tool.h
View File

@ -377,7 +377,6 @@
static XtensaConfigList node = { \
.config = &core, \
}; \
xtensa_finalize_config(&core); \
xtensa_register_core(&node); \
}
#else

2122
target/xtensa/translate.c
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File diff suppressed because it is too large Load Diff

22
target/xtensa/win_helper.c
View File

@ -96,9 +96,9 @@ void xtensa_rotate_window(CPUXtensaState *env, uint32_t delta)
xtensa_rotate_window_abs(env, env->sregs[WINDOW_BASE] + delta);
}
void HELPER(wsr_windowbase)(CPUXtensaState *env, uint32_t v)
void HELPER(sync_windowbase)(CPUXtensaState *env)
{
xtensa_rotate_window_abs(env, v);
xtensa_rotate_window_abs(env, env->windowbase_next);
}
void HELPER(entry)(CPUXtensaState *env, uint32_t pc, uint32_t s, uint32_t imm)
@ -106,9 +106,8 @@ void HELPER(entry)(CPUXtensaState *env, uint32_t pc, uint32_t s, uint32_t imm)
int callinc = (env->sregs[PS] & PS_CALLINC) >> PS_CALLINC_SHIFT;
env->regs[(callinc << 2) | (s & 3)] = env->regs[s] - imm;
xtensa_rotate_window(env, callinc);
env->sregs[WINDOW_START] |=
windowstart_bit(env->sregs[WINDOW_BASE], env);
env->windowbase_next = env->sregs[WINDOW_BASE] + callinc;
env->sregs[WINDOW_START] |= windowstart_bit(env->windowbase_next, env);
}
void HELPER(window_check)(CPUXtensaState *env, uint32_t pc, uint32_t w)
@ -185,20 +184,11 @@ void HELPER(test_underflow_retw)(CPUXtensaState *env, uint32_t pc)
}
}
uint32_t HELPER(retw)(CPUXtensaState *env, uint32_t pc)
void HELPER(retw)(CPUXtensaState *env, uint32_t a0)
{
int n = (env->regs[0] >> 30) & 0x3;
uint32_t windowbase = windowbase_bound(env->sregs[WINDOW_BASE], env);
uint32_t ret_pc = (pc & 0xc0000000) | (env->regs[0] & 0x3fffffff);
int n = (a0 >> 30) & 0x3;
xtensa_rotate_window(env, -n);
env->sregs[WINDOW_START] &= ~windowstart_bit(windowbase, env);
return ret_pc;
}
void HELPER(rotw)(CPUXtensaState *env, uint32_t imm4)
{
xtensa_rotate_window(env, imm4);
}
void xtensa_restore_owb(CPUXtensaState *env)

13
tests/tcg/xtensa/Makefile
View File

@ -18,6 +18,9 @@ CC = $(CROSS)gcc
AS = $(CROSS)gcc -x assembler-with-cpp
LD = $(CROSS)ld
ASFLAGS = -Wa,--no-absolute-literals
vectors_ASFLAGS = -mtext-section-literals
XTENSA_SRC_PATH = $(SRC_PATH)/tests/tcg/xtensa
INCLUDE_DIRS = $(XTENSA_SRC_PATH) $(SRC_PATH)/target/xtensa/core-$(CORE)
XTENSA_INC = $(addprefix -I,$(INCLUDE_DIRS))
@ -28,15 +31,21 @@ CRT = crt.o vectors.o
TESTCASES += test_b.tst
TESTCASES += test_bi.tst
#TESTCASES += test_boolean.tst
TESTCASES += test_boolean.tst
TESTCASES += test_break.tst
TESTCASES += test_bz.tst
TESTCASES += test_cache.tst
TESTCASES += test_clamps.tst
TESTCASES += test_extui.tst
TESTCASES += test_fail.tst
TESTCASES += test_flix.tst
TESTCASES += test_fp0_arith.tst
TESTCASES += test_fp0_conv.tst
TESTCASES += test_fp1.tst
TESTCASES += test_fp_cpenable.tst
TESTCASES += test_interrupt.tst
TESTCASES += test_loop.tst
TESTCASES += test_lsc.tst
TESTCASES += test_mac16.tst
TESTCASES += test_max.tst
TESTCASES += test_min.tst
@ -68,7 +77,7 @@ linker.ld: $(XTENSA_SRC_PATH)/linker.ld.S
$(CC) $(XTENSA_INC) $(CFLAGS) -c $< -o $@
%.o: $(XTENSA_SRC_PATH)/%.S
$(CC) $(XTENSA_INC) $(ASFLAGS) -c $< -o $@
$(CC) $(XTENSA_INC) $($*_ASFLAGS) $(ASFLAGS) -c $< -o $@
%.tst: %.o linker.ld $(XTENSA_SRC_PATH)/macros.inc $(CRT) Makefile
$(LD) $(LDFLAGS) $(NOSTDFLAGS) $(CRT) $< -o $@

67
tests/tcg/xtensa/linker.ld.S
View File

@ -1,17 +1,29 @@
#include "core-isa.h"
#if XTENSA_HAVE_BE
#ifndef XCHAL_VECBASE_RESET_VADDR
#define XCHAL_VECBASE_RESET_VADDR XCHAL_WINDOW_VECTORS_VADDR
#define XCHAL_WINDOW_OF4_VECOFS 0x00000000
#define XCHAL_WINDOW_UF4_VECOFS 0x00000040
#define XCHAL_WINDOW_OF8_VECOFS 0x00000080
#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
#define XCHAL_WINDOW_OF12_VECOFS 0x00000100
#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
#endif
#define RAM_SIZE 0x08000000 /* 128M */
#define ROM_SIZE 0x00001000 /* 4k */
#define VECTORS_RESERVED_SIZE 0x1000
#if XCHAL_HAVE_BE
OUTPUT_FORMAT("elf32-xtensa-be")
#else
OUTPUT_FORMAT("elf32-xtensa-le")
#endif
ENTRY(_start)
__DYNAMIC = 0;
MEMORY {
ram : ORIGIN = XCHAL_VECBASE_RESET_VADDR, LENGTH = 0x08000000 /* 128M */
rom : ORIGIN = XCHAL_RESET_VECTOR_VADDR, LENGTH = 0x00001000 /* 4k */
ram : ORIGIN = XCHAL_VECBASE_RESET_VADDR, LENGTH = RAM_SIZE
rom : ORIGIN = XCHAL_RESET_VECTOR_VADDR, LENGTH = ROM_SIZE
}
SECTIONS
@ -22,9 +34,9 @@ SECTIONS
*(.init.*)
} > rom
.vector :
{
#if XCHAL_HAVE_WINDOWED
.vector.window XCHAL_WINDOW_VECTORS_VADDR :
{
. = XCHAL_WINDOW_OF4_VECOFS;
*(.vector.window_overflow_4)
. = XCHAL_WINDOW_UF4_VECOFS;
@ -37,41 +49,58 @@ SECTIONS
*(.vector.window_overflow_12)
. = XCHAL_WINDOW_UF12_VECOFS;
*(.vector.window_underflow_12)
}
#endif
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 2
. = XCHAL_INTLEVEL2_VECOFS;
.vector.level2 XCHAL_INTLEVEL2_VECTOR_VADDR :
{
*(.vector.level2)
}
#endif
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 3
. = XCHAL_INTLEVEL3_VECOFS;
.vector.level3 XCHAL_INTLEVEL3_VECTOR_VADDR :
{
*(.vector.level3)
}
#endif
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 4
. = XCHAL_INTLEVEL4_VECOFS;
.vector.level4 XCHAL_INTLEVEL4_VECTOR_VADDR :
{
*(.vector.level4)
}
#endif
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 5
. = XCHAL_INTLEVEL5_VECOFS;
.vector.level5 XCHAL_INTLEVEL5_VECTOR_VADDR :
{
*(.vector.level5)
}
#endif
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 6
. = XCHAL_INTLEVEL6_VECOFS;
.vector.level6 XCHAL_INTLEVEL6_VECTOR_VADDR :
{
*(.vector.level6)
}
#endif
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 7
. = XCHAL_INTLEVEL7_VECOFS;
.vector.level7 XCHAL_INTLEVEL7_VECTOR_VADDR :
{
*(.vector.level7)
}
#endif
. = XCHAL_KERNEL_VECOFS;
.vector.kernel XCHAL_KERNEL_VECTOR_VADDR :
{
*(.vector.kernel)
. = XCHAL_USER_VECOFS;
}
.vector.user XCHAL_USER_VECTOR_VADDR :
{
*(.vector.user)
. = XCHAL_DOUBLEEXC_VECOFS;
}
.vector.double XCHAL_DOUBLEEXC_VECTOR_VADDR :
{
*(.vector.double)
} > ram
}
.vector.text :
.vector.text XCHAL_VECBASE_RESET_VADDR + VECTORS_RESERVED_SIZE :
{
*(.vector.window_overflow_4.*)
*(.vector.window_underflow_4.*)

41
tests/tcg/xtensa/macros.inc
View File

@ -23,11 +23,14 @@ main:
movi a0, result
sub a2, a2, a0
movi a3, 0
loopnez a2, 1f
l8ui a2, a0, 0
or a3, a3, a2
addi a0, a0, 1
beqz a2, 2f
1:
l8ui a1, a0, 0
or a3, a3, a1
addi a0, a0, 1
addi a2, a2, -1
bnez a2, 1b
2:
exit
.endm
@ -49,7 +52,9 @@ main:
.endm
.macro test name
//print test_\name
#ifdef DEBUG
print test_\name
#endif
test_init
test_\name:
.global test_\name
@ -74,6 +79,9 @@ test_\name:
l32i a2, a2, 0
movi a3, 1
s8i a3, a2, 0
#ifdef DEBUG
print failed
#endif
j 99f
.endm
@ -89,3 +97,26 @@ test_\name:
movi a3, \addr
s32i a3, a2, 0
.endm
.macro dump r
#ifdef DEBUG
.data
.align 4
1: .word 0
.text
movi a4, 1b
s32i a2, a4, 0
movi a2, 4
movi a3, 1
movi a5, 4
simcall
movi a4, 1b
l32i a2, a4, 0
#endif
.endm
#define glue(a, b) _glue(a, b)
#define _glue(a, b) a ## b
#define glue3(a, b, c) _glue3(a, b, c)
#define _glue3(a, b, c) a ## b ## c

40
tests/tcg/xtensa/test_b.S
View File

@ -84,12 +84,24 @@ test_end
test bbc
movi a2, 0xfffffffd
movi a3, 0xffffff01
#undef BIT
#if XCHAL_HAVE_BE
#define BIT 0xfffffffe
#else
#define BIT 0xffffff01
#endif
movi a3, BIT
bbc a2, a3, 1f
test_fail
1:
movi a2, 8
movi a3, 0xffffff03
#undef BIT
#if XCHAL_HAVE_BE
#define BIT 0xfffffffc
#else
#define BIT 0xffffff03
#endif
movi a3, BIT
bbc a2, a3, 1f
j 2f
1:
@ -99,11 +111,11 @@ test_end
test bbci
movi a2, 0xfffdffff
bbci a2, 17, 1f
bbci.l a2, 17, 1f
test_fail
1:
movi a2, 0x00020000
bbci a2, 17, 1f
bbci.l a2, 17, 1f
j 2f
1:
test_fail
@ -192,12 +204,24 @@ test_end
test bbs
movi a2, 8
movi a3, 0xffffff03
#undef BIT
#if XCHAL_HAVE_BE
#define BIT 0xfffffffc
#else
#define BIT 0xffffff03
#endif
movi a3, BIT
bbs a2, a3, 1f
test_fail
1:
movi a2, 0xfffffffd
movi a3, 0xffffff01
#undef BIT
#if XCHAL_HAVE_BE
#define BIT 0xfffffffe
#else
#define BIT 0xffffff01
#endif
movi a3, BIT
bbs a2, a3, 1f
j 2f
1:
@ -207,11 +231,11 @@ test_end
test bbsi
movi a2, 0x00020000
bbsi a2, 17, 1f
bbsi.l a2, 17, 1f
test_fail
1:
movi a2, 0xfffdffff
bbsi a2, 17, 1f
bbsi.l a2, 17, 1f
j 2f
1:
test_fail

4
tests/tcg/xtensa/test_boolean.S
View File

@ -2,6 +2,8 @@
test_suite boolean
#if XCHAL_HAVE_BOOLEANS
test all4
movi a2, 0xfec0
wsr a2, br
@ -20,4 +22,6 @@ test all4
assert eq, a2, a3
test_end
#endif
test_suite_end

27
tests/tcg/xtensa/test_break.S
View File

@ -1,10 +1,13 @@
#include "macros.inc"
#define debug_level 6
#define debug_vector level6
test_suite break
#if XCHAL_HAVE_DEBUG
#define debug_level XCHAL_DEBUGLEVEL
#define debug_vector glue(level, XCHAL_DEBUGLEVEL)
#define EPC_DEBUG glue(epc, XCHAL_DEBUGLEVEL)
test break
set_vector debug_vector, 0
rsil a2, debug_level
@ -21,7 +24,7 @@ test break
and a2, a2, a3
movi a3, 0x10 | debug_level
assert eq, a2, a3
rsr a2, epc6
rsr a2, EPC_DEBUG
movi a3, 1b
assert eq, a2, a3
rsr a2, debugcause
@ -45,7 +48,7 @@ test breakn
and a2, a2, a3
movi a3, 0x10 | debug_level
assert eq, a2, a3
rsr a2, epc6
rsr a2, EPC_DEBUG
movi a3, 1b
assert eq, a2, a3
rsr a2, debugcause
@ -53,6 +56,7 @@ test breakn
assert eq, a2, a3
test_end
#if XCHAL_NUM_IBREAK
test ibreak
set_vector debug_vector, 0
rsil a2, debug_level
@ -83,7 +87,7 @@ test ibreak
and a2, a2, a3
movi a3, 0x10 | debug_level
assert eq, a2, a3
rsr a2, epc6
rsr a2, EPC_DEBUG
movi a3, 1b
assert eq, a2, a3
rsr a2, debugcause
@ -110,7 +114,7 @@ test ibreak_remove
and a2, a2, a3
movi a3, 0x10 | debug_level
assert eq, a2, a3
rsr a2, epc6
rsr a2, EPC_DEBUG
movi a3, 2b
assert eq, a2, a3
rsr a2, debugcause
@ -141,6 +145,7 @@ test ibreak_priority
movi a3, 0x2
assert eq, a2, a3
test_end
#endif
test icount
set_vector debug_vector, 2f
@ -158,7 +163,7 @@ test icount
2:
movi a2, 0
wsr a2, icountlevel
rsr a2, epc6
rsr a2, EPC_DEBUG
movi a3, 1b
assert eq, a2, a3
rsr a2, debugcause
@ -167,7 +172,7 @@ test icount
test_end
.macro check_dbreak dr
rsr a2, epc6
rsr a2, EPC_DEBUG
movi a3, 1b
assert eq, a2, a3
rsr a2, debugcause
@ -194,6 +199,7 @@ test_end
reset_ps
.endm
#if XCHAL_NUM_DBREAK
test dbreak_exact
dbreak_test 0, 0x4000003f, 0xd000007f, 0xd000007f, l8ui
dbreak_test 1, 0x4000003e, 0xd000007e, 0xd000007e, l16ui
@ -253,5 +259,8 @@ test dbreak_invalid
dbreak_test 0, 0x40000030, 0xd0000071, 0xd0000070, l16ui
dbreak_test 1, 0x40000035, 0xd0000072, 0xd0000070, l32i
test_end
#endif
#endif
test_suite_end

66
tests/tcg/xtensa/test_cache.S
View File

@ -7,6 +7,8 @@
test_suite cache
#if XCHAL_HAVE_PTP_MMU
.macro pf_op op
\op a2, 0
\op a3, 0
@ -18,14 +20,23 @@ test prefetch
movi a3, 0xd8000000 /* non-cacheable */
movi a4, 0x00001235 /* unmapped */
#if XCHAL_DCACHE_SIZE
pf_op dpfr
pf_op dpfro
pf_op dpfw
pf_op dpfwo
#endif
#ifdef XCHAL_ICACHE_SIZE
pf_op ipf
#endif
#if XCHAL_HAVE_PTP_MMU && !XCHAL_HAVE_SPANNING_WAY
#if XCHAL_DCACHE_LINE_LOCKABLE
dpfl a2, 0
#endif
#if XCHAL_ICACHE_LINE_LOCKABLE
ipfl a2, 0
#endif
#endif
test_end
.macro cache_fault op, addr, exc_code
@ -46,10 +57,16 @@ test_end
assert eq, a2, a3
.endm
#if XCHAL_HAVE_PTP_MMU && !XCHAL_HAVE_SPANNING_WAY
#if XCHAL_DCACHE_LINE_LOCKABLE
test dpfl_tlb_miss
cache_fault dpfl, 0x00002345, 24
test_end
#endif
#if XCHAL_DCACHE_SIZE
#if XCHAL_DCACHE_IS_WRITEBACK
test dhwb_tlb_miss
cache_fault dhwb, 0x00002345, 24
test_end
@ -57,16 +74,21 @@ test_end
test dhwbi_tlb_miss
cache_fault dhwbi, 0x00002345, 24
test_end
#endif
test dhi_tlb_miss
cache_fault dhi, 0x00002345, 24
test_end
#if XCHAL_DCACHE_LINE_LOCKABLE
test dhu_tlb_miss
cache_fault dhu, 0x00002345, 24
test_end
#endif
#endif
#if XCHAL_ICACHE_SIZE
#if XCHAL_ICACHE_LINE_LOCKABLE
test ipfl_tlb_miss
cache_fault ipfl, 0x00002345, 16
test_end
@ -74,24 +96,40 @@ test_end
test ihu_tlb_miss
cache_fault ihu, 0x00002345, 16
test_end
#endif
test ihi_tlb_miss
cache_fault ihi, 0x00002345, 16
test_end
#endif
#endif
#endif
test_suite_end
.macro cache_all op1, op2, size, linesize
movi a2, 0
movi a3, \size
1:
\op1 a2, 0
\op2 a2, 0
addi a2, a2, \linesize
bltu a2, a3, 1b
.endm
cache_unlock_invalidate:
cache_all diu, dii, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE
cache_all iiu, iii, XCHAL_ICACHE_SIZE, XCHAL_ICACHE_LINESIZE
#if XCHAL_DCACHE_SIZE
movi a2, 0
movi a3, XCHAL_DCACHE_SIZE
1:
#if XCHAL_DCACHE_LINE_LOCKABLE
diu a2, 0
#endif
dii a2, 0
addi a2, a2, XCHAL_DCACHE_LINESIZE
bltu a2, a3, 1b
#endif
#if XCHAL_ICACHE_SIZE
movi a2, 0
movi a3, XCHAL_ICACHE_SIZE
1:
#if XCHAL_ICACHE_LINE_LOCKABLE
iiu a2, 0
#endif
iii a2, 0
addi a2, a2, XCHAL_ICACHE_LINESIZE
bltu a2, a3, 1b
#endif
ret

4
tests/tcg/xtensa/test_clamps.S
View File

@ -2,6 +2,8 @@
test_suite clamps
#if XCHAL_HAVE_CLAMPS
test clamps
movi a2, 0
movi a3, 0
@ -39,4 +41,6 @@ test clamps
assert eq, a3, a2
test_end
#endif
test_suite_end

60
tests/tcg/xtensa/test_flix.S Normal file
View File

@ -0,0 +1,60 @@
#include "macros.inc"
test_suite flix
#if XCHAL_HAVE_FLIX3
test misc
{
mov a3, a4
mov a2, a3
nop
}
{
nop
bne.w18 a2, a3, 1f
}
movi a2, 1f
{
mov a2, a3
mov a3, a2
nop
}
{
l32i a2, a3, 0
add a4, a4, a2
nop
}
{
mov a3, a4
jx a3
nop
}
1:
test_end
test sum
movi a2, 0
movi a3, 2f
movi a4, 0
movi a5, 4
loop a5, 1f
{
l32i a2, a3, 0
addi a3, a3, 4
add a4, a4, a2
}
1:
add a4, a4, a2
assert eqi, a4, 10
.data
2:
.word 1, 2, 3, 4
.previous
test_end
#endif
test_suite_end

173
tests/tcg/xtensa/test_fp0_arith.S Normal file
View File

@ -0,0 +1,173 @@
#include "macros.inc"
test_suite fp0_arith
#if XCHAL_HAVE_FP
.macro movfp fr, v
movi a2, \v
wfr \fr, a2
.endm
.macro check_res fr, r
rfr a2, \fr
dump a2
movi a3, \r
assert eq, a2, a3
rur a2, fsr
assert eqi, a2, 0
.endm
.macro test_op2_rm op, fr0, fr1, fr2, v0, v1, r
movi a2, 0
wur a2, fsr
movfp \fr0, \v0
movfp \fr1, \v1
\op \fr2, \fr0, \fr1
check_res \fr2, \r
.endm
.macro test_op3_rm op, fr0, fr1, fr2, fr3, v0, v1, v2, r
movi a2, 0
wur a2, fsr
movfp \fr0, \v0
movfp \fr1, \v1
movfp \fr2, \v2
\op \fr0, \fr1, \fr2
check_res \fr3, \r
.endm
.macro test_op2_ex op, fr0, fr1, fr2, v0, v1, rm, r
movi a2, \rm
wur a2, fcr
test_op2_rm \op, \fr0, \fr1, \fr2, \v0, \v1, \r
movi a2, (\rm) | 0x7c
wur a2, fcr
test_op2_rm \op, \fr0, \fr1, \fr2, \v0, \v1, \r
.endm
.macro test_op3_ex op, fr0, fr1, fr2, fr3, v0, v1, v2, rm, r
movi a2, \rm
wur a2, fcr
test_op3_rm \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, \r
movi a2, (\rm) | 0x7c
wur a2, fcr
test_op3_rm \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, \r
.endm
.macro test_op2 op, fr0, fr1, fr2, v0, v1, r0, r1, r2, r3
test_op2_ex \op, \fr0, \fr1, \fr2, \v0, \v1, 0, \r0
test_op2_ex \op, \fr0, \fr1, \fr2, \v0, \v1, 1, \r1
test_op2_ex \op, \fr0, \fr1, \fr2, \v0, \v1, 2, \r2
test_op2_ex \op, \fr0, \fr1, \fr2, \v0, \v1, 3, \r3
.endm
.macro test_op3 op, fr0, fr1, fr2, fr3, v0, v1, v2, r0, r1, r2, r3
test_op3_ex \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, 0, \r0
test_op3_ex \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, 1, \r1
test_op3_ex \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, 2, \r2
test_op3_ex \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, 3, \r3
.endm
.macro test_op2_cpe op
set_vector kernel, 2f
movi a2, 0
wsr a2, cpenable
1:
\op f2, f0, f1
test_fail
2:
rsr a2, excvaddr
movi a3, 1b
assert eq, a2, a3
rsr a2, exccause
movi a3, 32
assert eq, a2, a3
set_vector kernel, 0
movi a2, 1
wsr a2, cpenable
.endm
test add_s
movi a2, 1
wsr a2, cpenable
test_op2 add.s, f0, f1, f2, 0x3fc00000, 0x34400000, \
0x3fc00002, 0x3fc00001, 0x3fc00002, 0x3fc00001
test_op2 add.s, f3, f4, f5, 0x3fc00000, 0x34a00000, \
0x3fc00002, 0x3fc00002, 0x3fc00003, 0x3fc00002
/* MAX_FLOAT + MAX_FLOAT = +inf/MAX_FLOAT */
test_op2 add.s, f6, f7, f8, 0x7f7fffff, 0x7f7fffff, \
0x7f800000, 0x7f7fffff, 0x7f800000, 0x7f7fffff
test_end
test add_s_inf
/* 1 + +inf = +inf */
test_op2 add.s, f6, f7, f8, 0x3fc00000, 0x7f800000, \
0x7f800000, 0x7f800000, 0x7f800000, 0x7f800000
/* +inf + -inf = default NaN */
test_op2 add.s, f0, f1, f2, 0x7f800000, 0xff800000, \
0x7fc00000, 0x7fc00000, 0x7fc00000, 0x7fc00000
test_end
test add_s_nan
/* 1 + NaN = NaN */
test_op2 add.s, f9, f10, f11, 0x3fc00000, 0x7fc00001, \
0x7fc00001, 0x7fc00001, 0x7fc00001, 0x7fc00001
test_op2 add.s, f12, f13, f14, 0x3fc00000, 0x7f800001, \
0x7f800001, 0x7f800001, 0x7f800001, 0x7f800001
/* NaN1 + NaN2 = NaN1 */
test_op2 add.s, f15, f0, f1, 0x7f800001, 0x7fbfffff, \
0x7f800001, 0x7f800001, 0x7f800001, 0x7f800001
test_op2 add.s, f2, f3, f4, 0x7fbfffff, 0x7f800001, \
0x7fbfffff, 0x7fbfffff, 0x7fbfffff, 0x7fbfffff
test_op2 add.s, f5, f6, f7, 0x7fc00001, 0x7fbfffff, \
0x7fc00001, 0x7fc00001, 0x7fc00001, 0x7fc00001
test_op2 add.s, f8, f9, f10, 0x7fbfffff, 0x7fc00001, \
0x7fbfffff, 0x7fbfffff, 0x7fbfffff, 0x7fbfffff
test_end
test sub_s
test_op2 sub.s, f0, f1, f0, 0x3f800001, 0x33800000, \
0x3f800000, 0x3f800000, 0x3f800001, 0x3f800000
test_op2 sub.s, f0, f1, f1, 0x3f800002, 0x33800000, \
0x3f800002, 0x3f800001, 0x3f800002, 0x3f800001
/* norm - norm = denorm */
test_op2 sub.s, f6, f7, f8, 0x00800001, 0x00800000, \
0x00000001, 0x00000001, 0x00000001, 0x00000001
test_end
test mul_s
test_op2 mul.s, f0, f1, f2, 0x3f800001, 0x3f800001, \
0x3f800002, 0x3f800002, 0x3f800003, 0x3f800002
/* MAX_FLOAT/2 * MAX_FLOAT/2 = +inf/MAX_FLOAT */
test_op2 mul.s, f6, f7, f8, 0x7f000000, 0x7f000000, \
0x7f800000, 0x7f7fffff, 0x7f800000, 0x7f7fffff
/* min norm * min norm = 0/denorm */
test_op2 mul.s, f6, f7, f8, 0x00800001, 0x00800000, \
0x00000000, 0x00000000, 0x00000001, 0x00000000
/* inf * 0 = default NaN */
test_op2 mul.s, f6, f7, f8, 0x7f800000, 0x00000000, \
0x7fc00000, 0x7fc00000, 0x7fc00000, 0x7fc00000
test_end
test madd_s
test_op3 madd.s, f0, f1, f2, f0, 0, 0x3f800001, 0x3f800001, \
0x3f800002, 0x3f800002, 0x3f800003, 0x3f800002
test_end
test msub_s
test_op3 msub.s, f0, f1, f2, f0, 0x3f800000, 0x3f800001, 0x3f800001, \
0xb4800000, 0xb4800000, 0xb4800000, 0xb4800001
test_end
#endif
test_suite_end

304
tests/tcg/xtensa/test_fp0_conv.S Normal file
View File

@ -0,0 +1,304 @@
#include "macros.inc"
test_suite fp0_conv
#if XCHAL_HAVE_FP
.macro movfp fr, v
movi a2, \v
wfr \fr, a2
.endm
.macro test_ftoi_ex op, r0, fr0, v, c, r
movi a2, 0
wur a2, fsr
movfp \fr0, \v
\op \r0, \fr0, \c
dump \r0
movi a3, \r
assert eq, \r0, a3
rur a2, fsr
assert eqi, a2, 0
.endm
.macro test_ftoi op, r0, fr0, v, c, r
movi a2, 0
wur a2, fcr
test_ftoi_ex \op, \r0, \fr0, \v, \c, \r
movi a2, 0x7c
wur a2, fcr
test_ftoi_ex \op, \r0, \fr0, \v, \c, \r
.endm
.macro test_itof_ex op, fr0, ar0, v, c, r
movi a2, 0
wur a2, fsr
movi \ar0, \v
\op \fr0, \ar0, \c
rfr a2, \fr0
dump a2
movi a3, \r
assert eq, a2, a3
rur a2, fsr
assert eqi, a2, 0
.endm
.macro test_itof_rm op, fr0, ar0, v, c, rm, r
movi a2, \rm
wur a2, fcr
test_itof_ex \op, \fr0, \ar0, \v, \c, \r
movi a2, (\rm) | 0x7c
wur a2, fcr
test_itof_ex \op, \fr0, \ar0, \v, \c, \r
.endm
.macro test_itof op, fr0, ar0, v, c, r0, r1, r2, r3
test_itof_rm \op, \fr0, \ar0, \v, \c, 0, \r0
test_itof_rm \op, \fr0, \ar0, \v, \c, 1, \r1
test_itof_rm \op, \fr0, \ar0, \v, \c, 2, \r2
test_itof_rm \op, \fr0, \ar0, \v, \c, 3, \r3
.endm
test round_s
movi a2, 1
wsr a2, cpenable
/* NaN */
test_ftoi round.s, a2, f0, 0xffc00001, 0, 0x7fffffff
test_ftoi round.s, a2, f0, 0xff800001, 0, 0x7fffffff
/* -inf */
test_ftoi round.s, a2, f0, 0xff800000, 0, 0x80000000
/* negative overflow */
test_ftoi round.s, a2, f0, 0xceffffff, 1, 0x80000000
test_ftoi round.s, a2, f0, 0xcf000000, 0, 0x80000000
test_ftoi round.s, a2, f0, 0xceffffff, 0, 0x80000080
/* negative */
test_ftoi round.s, a2, f0, 0xbfa00000, 1, -2 /* -1.25 * 2 */
test_ftoi round.s, a2, f0, 0xbfc00000, 0, -2 /* -1.5 */
test_ftoi round.s, a2, f0, 0xbf800000, 1, -2 /* -1 * 2 */
test_ftoi round.s, a2, f0, 0xbf800000, 0, -1 /* -1 */
test_ftoi round.s, a2, f0, 0xbf400000, 0, -1 /* -0.75 */
test_ftoi round.s, a2, f0, 0xbf000000, 0, 0 /* -0.5 */
/* positive */
test_ftoi round.s, a2, f0, 0x3f000000, 0, 0 /* 0.5 */
test_ftoi round.s, a2, f0, 0x3f400000, 0, 1 /* 0.75 */
test_ftoi round.s, a2, f0, 0x3f800000, 0, 1 /* 1 */
test_ftoi round.s, a2, f0, 0x3f800000, 1, 2 /* 1 * 2 */
test_ftoi round.s, a2, f0, 0x3fc00000, 0, 2 /* 1.5 */
test_ftoi round.s, a2, f0, 0x3fa00000, 1, 2 /* 1.25 * 2 */
/* positive overflow */
test_ftoi round.s, a2, f0, 0x4effffff, 0, 0x7fffff80
test_ftoi round.s, a2, f0, 0x4f000000, 0, 0x7fffffff
test_ftoi round.s, a2, f0, 0x4effffff, 1, 0x7fffffff
/* +inf */
test_ftoi round.s, a2, f0, 0x7f800000, 0, 0x7fffffff
/* NaN */
test_ftoi round.s, a2, f0, 0x7f800001, 0, 0x7fffffff
test_ftoi round.s, a2, f0, 0x7fc00000, 0, 0x7fffffff
test_end
test trunc_s
/* NaN */
test_ftoi trunc.s, a2, f0, 0xffc00001, 0, 0x7fffffff
test_ftoi trunc.s, a2, f0, 0xff800001, 0, 0x7fffffff
/* -inf */
test_ftoi trunc.s, a2, f0, 0xff800000, 0, 0x80000000
/* negative overflow */
test_ftoi trunc.s, a2, f0, 0xceffffff, 1, 0x80000000
test_ftoi trunc.s, a2, f0, 0xcf000000, 0, 0x80000000
test_ftoi trunc.s, a2, f0, 0xceffffff, 0, 0x80000080
/* negative */
test_ftoi trunc.s, a2, f0, 0xbfa00000, 1, -2 /* -1.25 * 2 */
test_ftoi trunc.s, a2, f0, 0xbfc00000, 0, -1 /* -1.5 */
test_ftoi trunc.s, a2, f0, 0xbf800000, 1, -2 /* -1 * 2 */
test_ftoi trunc.s, a2, f0, 0xbf800000, 0, -1 /* -1 */
test_ftoi trunc.s, a2, f0, 0xbf400000, 0, 0 /* -0.75 */
test_ftoi trunc.s, a2, f0, 0xbf000000, 0, 0 /* -0.5 */
/* positive */
test_ftoi trunc.s, a2, f0, 0x3f000000, 0, 0 /* 0.5 */
test_ftoi trunc.s, a2, f0, 0x3f400000, 0, 0 /* 0.75 */
test_ftoi trunc.s, a2, f0, 0x3f800000, 0, 1 /* 1 */
test_ftoi trunc.s, a2, f0, 0x3f800000, 1, 2 /* 1 * 2 */
test_ftoi trunc.s, a2, f0, 0x3fc00000, 0, 1 /* 1.5 */
test_ftoi trunc.s, a2, f0, 0x3fa00000, 1, 2 /* 1.25 * 2 */
/* positive overflow */
test_ftoi trunc.s, a2, f0, 0x4effffff, 0, 0x7fffff80
test_ftoi trunc.s, a2, f0, 0x4f000000, 0, 0x7fffffff
test_ftoi trunc.s, a2, f0, 0x4effffff, 1, 0x7fffffff
/* +inf */
test_ftoi trunc.s, a2, f0, 0x7f800000, 0, 0x7fffffff
/* NaN */
test_ftoi trunc.s, a2, f0, 0x7f800001, 0, 0x7fffffff
test_ftoi trunc.s, a2, f0, 0x7fc00000, 0, 0x7fffffff
test_end
test floor_s
/* NaN */
test_ftoi floor.s, a2, f0, 0xffc00001, 0, 0x7fffffff
test_ftoi floor.s, a2, f0, 0xff800001, 0, 0x7fffffff
/* -inf */
test_ftoi floor.s, a2, f0, 0xff800000, 0, 0x80000000
/* negative overflow */
test_ftoi floor.s, a2, f0, 0xceffffff, 1, 0x80000000
test_ftoi floor.s, a2, f0, 0xcf000000, 0, 0x80000000
test_ftoi floor.s, a2, f0, 0xceffffff, 0, 0x80000080
/* negative */
test_ftoi floor.s, a2, f0, 0xbfa00000, 1, -3 /* -1.25 * 2 */
test_ftoi floor.s, a2, f0, 0xbfc00000, 0, -2 /* -1.5 */
test_ftoi floor.s, a2, f0, 0xbf800000, 1, -2 /* -1 * 2 */
test_ftoi floor.s, a2, f0, 0xbf800000, 0, -1 /* -1 */
test_ftoi floor.s, a2, f0, 0xbf400000, 0, -1 /* -0.75 */
test_ftoi floor.s, a2, f0, 0xbf000000, 0, -1 /* -0.5 */
/* positive */
test_ftoi floor.s, a2, f0, 0x3f000000, 0, 0 /* 0.5 */
test_ftoi floor.s, a2, f0, 0x3f400000, 0, 0 /* 0.75 */
test_ftoi floor.s, a2, f0, 0x3f800000, 0, 1 /* 1 */
test_ftoi floor.s, a2, f0, 0x3f800000, 1, 2 /* 1 * 2 */
test_ftoi floor.s, a2, f0, 0x3fc00000, 0, 1 /* 1.5 */
test_ftoi floor.s, a2, f0, 0x3fa00000, 1, 2 /* 1.25 * 2 */
/* positive overflow */
test_ftoi floor.s, a2, f0, 0x4effffff, 0, 0x7fffff80
test_ftoi floor.s, a2, f0, 0x4f000000, 0, 0x7fffffff
test_ftoi floor.s, a2, f0, 0x4effffff, 1, 0x7fffffff
/* +inf */
test_ftoi floor.s, a2, f0, 0x7f800000, 0, 0x7fffffff
/* NaN */
test_ftoi floor.s, a2, f0, 0x7f800001, 0, 0x7fffffff
test_ftoi floor.s, a2, f0, 0x7fc00000, 0, 0x7fffffff
test_end
test ceil_s
/* NaN */
test_ftoi ceil.s, a2, f0, 0xffc00001, 0, 0x7fffffff
test_ftoi ceil.s, a2, f0, 0xff800001, 0, 0x7fffffff
/* -inf */
test_ftoi ceil.s, a2, f0, 0xff800000, 0, 0x80000000
/* negative overflow */
test_ftoi ceil.s, a2, f0, 0xceffffff, 1, 0x80000000
test_ftoi ceil.s, a2, f0, 0xcf000000, 0, 0x80000000
test_ftoi ceil.s, a2, f0, 0xceffffff, 0, 0x80000080
/* negative */
test_ftoi ceil.s, a2, f0, 0xbfa00000, 1, -2 /* -1.25 * 2 */
test_ftoi ceil.s, a2, f0, 0xbfc00000, 0, -1 /* -1.5 */
test_ftoi ceil.s, a2, f0, 0xbf800000, 1, -2 /* -1 * 2 */
test_ftoi ceil.s, a2, f0, 0xbf800000, 0, -1 /* -1 */
test_ftoi ceil.s, a2, f0, 0xbf400000, 0, 0 /* -0.75 */
test_ftoi ceil.s, a2, f0, 0xbf000000, 0, 0 /* -0.5 */
/* positive */
test_ftoi ceil.s, a2, f0, 0x3f000000, 0, 1 /* 0.5 */
test_ftoi ceil.s, a2, f0, 0x3f400000, 0, 1 /* 0.75 */
test_ftoi ceil.s, a2, f0, 0x3f800000, 0, 1 /* 1 */
test_ftoi ceil.s, a2, f0, 0x3f800000, 1, 2 /* 1 * 2 */
test_ftoi ceil.s, a2, f0, 0x3fc00000, 0, 2 /* 1.5 */
test_ftoi ceil.s, a2, f0, 0x3fa00000, 1, 3 /* 1.25 * 2 */
/* positive overflow */
test_ftoi ceil.s, a2, f0, 0x4effffff, 0, 0x7fffff80
test_ftoi ceil.s, a2, f0, 0x4f000000, 0, 0x7fffffff
test_ftoi ceil.s, a2, f0, 0x4effffff, 1, 0x7fffffff
/* +inf */
test_ftoi ceil.s, a2, f0, 0x7f800000, 0, 0x7fffffff
/* NaN */
test_ftoi ceil.s, a2, f0, 0x7f800001, 0, 0x7fffffff
test_ftoi ceil.s, a2, f0, 0x7fc00000, 0, 0x7fffffff
test_end
test utrunc_s
/* NaN */
test_ftoi utrunc.s, a2, f0, 0xffc00001, 0, 0xffffffff
test_ftoi utrunc.s, a2, f0, 0xff800001, 0, 0xffffffff
/* -inf */
test_ftoi utrunc.s, a2, f0, 0xff800000, 0, 0x80000000
/* negative overflow */
test_ftoi utrunc.s, a2, f0, 0xceffffff, 1, 0x80000000
test_ftoi utrunc.s, a2, f0, 0xcf000000, 0, 0x80000000
test_ftoi utrunc.s, a2, f0, 0xceffffff, 0, 0x80000080
/* negative */
test_ftoi utrunc.s, a2, f0, 0xbfa00000, 1, -2 /* -1.25 * 2 */
test_ftoi utrunc.s, a2, f0, 0xbfc00000, 0, -1 /* -1.5 */
test_ftoi utrunc.s, a2, f0, 0xbf800000, 1, -2 /* -1 * 2 */
test_ftoi utrunc.s, a2, f0, 0xbf800000, 0, -1 /* -1 */
test_ftoi utrunc.s, a2, f0, 0xbf400000, 0, 0 /* -0.75 */
test_ftoi utrunc.s, a2, f0, 0xbf000000, 0, 0 /* -0.5 */
/* positive */
test_ftoi utrunc.s, a2, f0, 0x3f000000, 0, 0 /* 0.5 */
test_ftoi utrunc.s, a2, f0, 0x3f400000, 0, 0 /* 0.75 */
test_ftoi utrunc.s, a2, f0, 0x3f800000, 0, 1 /* 1 */
test_ftoi utrunc.s, a2, f0, 0x3f800000, 1, 2 /* 1 * 2 */
test_ftoi utrunc.s, a2, f0, 0x3fc00000, 0, 1 /* 1.5 */
test_ftoi utrunc.s, a2, f0, 0x3fa00000, 1, 2 /* 1.25 * 2 */
/* positive overflow */
test_ftoi utrunc.s, a2, f0, 0x4effffff, 0, 0x7fffff80
test_ftoi utrunc.s, a2, f0, 0x4f000000, 0, 0x80000000
test_ftoi utrunc.s, a2, f0, 0x4effffff, 1, 0xffffff00
test_ftoi utrunc.s, a2, f0, 0x4f800000, 1, 0xffffffff
/* +inf */
test_ftoi utrunc.s, a2, f0, 0x7f800000, 0, 0xffffffff
/* NaN */
test_ftoi utrunc.s, a2, f0, 0x7f800001, 0, 0xffffffff
test_ftoi utrunc.s, a2, f0, 0x7fc00000, 0, 0xffffffff
test_end
test float_s
test_itof float.s, f0, a2, -1, 0, \
0xbf800000, 0xbf800000, 0xbf800000, 0xbf800000
test_itof float.s, f0, a2, 0, 0, 0, 0, 0, 0
test_itof float.s, f0, a2, 1, 1, \
0x3f000000, 0x3f000000, 0x3f000000, 0x3f000000
test_itof float.s, f0, a2, 1, 0, \
0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000
test_itof float.s, f0, a2, 0x7fffffff, 0, \
0x4f000000, 0x4effffff, 0x4f000000, 0x4effffff
test_end
test ufloat_s
test_itof ufloat.s, f0, a2, 0, 0, 0, 0, 0, 0
test_itof ufloat.s, f0, a2, 1, 1, \
0x3f000000, 0x3f000000, 0x3f000000, 0x3f000000
test_itof ufloat.s, f0, a2, 1, 0, \
0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000
test_itof ufloat.s, f0, a2, 0x7fffffff, 0, \
0x4f000000, 0x4effffff, 0x4f000000, 0x4effffff
test_itof ufloat.s, f0, a2, 0xffffffff, 0, \
0x4f800000, 0x4f7fffff, 0x4f800000, 0x4f7fffff
test_end
#endif
test_suite_end

141
tests/tcg/xtensa/test_fp1.S Normal file
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@ -0,0 +1,141 @@
#include "macros.inc"
test_suite fp1
#if XCHAL_HAVE_FP
.macro movfp fr, v
movi a2, \v
wfr \fr, a2
.endm
.macro test_ord_ex op, br, fr0, fr1, v0, v1, r
movi a2, 0
wur a2, fsr
movfp \fr0, \v0
movfp \fr1, \v1
\op \br, \fr0, \fr1
movi a2, 0
movi a3, 1
movt a2, a3, \br
assert eqi, a2, \r
rur a2, fsr
assert eqi, a2, 0
.endm
.macro test_ord op, br, fr0, fr1, v0, v1, r
movi a2, 0
wur a2, fcr
test_ord_ex \op, \br, \fr0, \fr1, \v0, \v1, \r
movi a2, 0x7c
wur a2, fcr
test_ord_ex \op, \br, \fr0, \fr1, \v0, \v1, \r
.endm
.macro test_ord_all op, aa, ab, ba, aPI, PIa, aN, Na, II, IN, NI
test_ord \op b0, f0, f1, 0x3f800000, 0x3f800000, \aa
test_ord \op b1, f2, f3, 0x3f800000, 0x3fc00000, \ab
test_ord \op b2, f4, f5, 0x3fc00000, 0x3f800000, \ba
test_ord \op b3, f6, f7, 0x3f800000, 0x7f800000, \aPI
test_ord \op b4, f8, f9, 0x7f800000, 0x3f800000, \PIa
test_ord \op b5, f10, f11, 0x3f800000, 0xffc00001, \aN
test_ord \op b6, f12, f13, 0x3f800000, 0xff800001, \aN
test_ord \op b7, f14, f15, 0x3f800000, 0x7f800001, \aN
test_ord \op b8, f0, f1, 0x3f800000, 0x7fc00000, \aN
test_ord \op b9, f2, f3, 0xffc00001, 0x3f800000, \Na
test_ord \op b10, f4, f5, 0xff800001, 0x3f800000, \Na
test_ord \op b11, f6, f7, 0x7f800001, 0x3f800000, \Na
test_ord \op b12, f8, f9, 0x7fc00000, 0x3f800000, \Na
test_ord \op b13, f10, f11, 0x7f800000, 0x7f800000, \II
test_ord \op b14, f12, f13, 0x7f800000, 0x7fc00000, \IN
test_ord \op b15, f14, f15, 0x7fc00000, 0x7f800000, \NI
.endm
test un_s
movi a2, 1
wsr a2, cpenable
test_ord_all un.s, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1
test_end
test oeq_s
test_ord_all oeq.s, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0
test_end
test ueq_s
test_ord_all ueq.s, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1
test_end
test olt_s
test_ord_all olt.s, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0
test_end
test ult_s
test_ord_all ult.s, 0, 1, 0, 1, 0, 1, 1, 0, 1, 1
test_end
test ole_s
test_ord_all ole.s, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0
test_end
test ule_s
test_ord_all ule.s, 1, 1, 0, 1, 0, 1, 1, 1, 1, 1
test_end
.macro test_cond op, fr0, fr1, cr, v0, v1, r
movfp \fr0, \v0
movfp \fr1, \v1
\op \fr0, \fr1, \cr
rfr a2, \fr0
movi a3, \r
assert eq, a2, a3
.endm
test moveqz_s
movi a3, 0
test_cond moveqz.s, f0, f1, a3, 0, 0x3f800000, 0x3f800000
movi a3, 1
test_cond moveqz.s, f0, f1, a3, 0, 0x3f800000, 0
test_end
test movnez_s
movi a3, 0
test_cond movnez.s, f0, f1, a3, 0, 0x3f800000, 0
movi a3, 1
test_cond movnez.s, f0, f1, a3, 0, 0x3f800000, 0x3f800000
test_end
test movltz_s
movi a3, -1
test_cond movltz.s, f0, f1, a3, 0, 0x3f800000, 0x3f800000
movi a3, 0
test_cond movltz.s, f0, f1, a3, 0, 0x3f800000, 0
movi a3, 1
test_cond movltz.s, f0, f1, a3, 0, 0x3f800000, 0
test_end
test movgez_s
movi a3, -1
test_cond movgez.s, f0, f1, a3, 0, 0x3f800000, 0
movi a3, 0
test_cond movgez.s, f0, f1, a3, 0, 0x3f800000, 0x3f800000
movi a3, 1
test_cond movgez.s, f0, f1, a3, 0, 0x3f800000, 0x3f800000
test_end
test movf_s
olt.s b0, f0, f0
test_cond movf.s, f0, f1, b0, 0, 0x3f800000, 0x3f800000
ueq.s b0, f0, f0
test_cond movf.s, f0, f1, b0, 0, 0x3f800000, 0
test_end
test movt_s
ueq.s b0, f0, f0
test_cond movt.s, f0, f1, b0, 0, 0x3f800000, 0x3f800000
olt.s b0, f0, f0
test_cond movt.s, f0, f1, b0, 0, 0x3f800000, 0
test_end
#endif
test_suite_end

27
tests/tcg/xtensa/test_fp_cpenable.S Normal file
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@ -0,0 +1,27 @@
#include "macros.inc"
test_suite fp_cpenable
#if XCHAL_HAVE_FP
test rur
set_vector kernel, 2f
movi a2, 0
wsr a2, cpenable
isync
1:
rur a2, fsr
//wfr f0, a2
test_fail
2:
movi a2, 1b
rsr a3, epc1
assert eq, a2, a3
movi a2, 32
rsr a3, exccause
assert eq, a2, a3
test_end
#endif
test_suite_end

88
tests/tcg/xtensa/test_interrupt.S
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@ -1,15 +1,59 @@
#include "macros.inc"
#define LSBIT(v) ((v) ^ ((v) & ((v) - 1)))
#define LSBIT(v) ((v) & -(v))
#define LEVEL_MASK(x) glue3(XCHAL_INTLEVEL, x, _MASK)
#define LEVEL_SOFT_MASK(x) (LEVEL_MASK(x) & XCHAL_INTTYPE_MASK_SOFTWARE)
#define L1_SOFT_MASK LEVEL_SOFT_MASK(1)
#define L1_SOFT LSBIT(L1_SOFT_MASK)
#if LEVEL_SOFT_MASK(2)
#define HIGH_LEVEL_SOFT_MASK LEVEL_SOFT_MASK(2)
#elif LEVEL_SOFT_MASK(3)
#define HIGH_LEVEL_SOFT_MASK LEVEL_SOFT_MASK(3)
#elif LEVEL_SOFT_MASK(4)
#define HIGH_LEVEL_SOFT_MASK LEVEL_SOFT_MASK(4)
#elif LEVEL_SOFT_MASK(5)
#define HIGH_LEVEL_SOFT_MASK LEVEL_SOFT_MASK(5)
#elif LEVEL_SOFT_MASK(6)
#define HIGH_LEVEL_SOFT_MASK LEVEL_SOFT_MASK(6)
#else
#define HIGH_LEVEL_SOFT_MASK 0
#endif
#define HIGH_LEVEL_SOFT LSBIT(HIGH_LEVEL_SOFT_MASK)
#if LEVEL_SOFT_MASK(2)
#define HIGH_LEVEL_SOFT_LEVEL 2
#elif LEVEL_SOFT_MASK(3)
#define HIGH_LEVEL_SOFT_LEVEL 3
#elif LEVEL_SOFT_MASK(4)
#define HIGH_LEVEL_SOFT_LEVEL 4
#elif LEVEL_SOFT_MASK(5)
#define HIGH_LEVEL_SOFT_LEVEL 5
#elif LEVEL_SOFT_MASK(6)
#define HIGH_LEVEL_SOFT_LEVEL 6
#else
#define HIGH_LEVEL_SOFT_LEVEL 0
#endif
test_suite interrupt
#if XCHAL_HAVE_INTERRUPTS
.macro clear_interrupts
movi a2, 0
wsr a2, intenable
#if XCHAL_NUM_TIMERS
wsr a2, ccompare0
#endif
#if XCHAL_NUM_TIMERS > 1
wsr a2, ccompare1
#endif
#if XCHAL_NUM_TIMERS > 2
wsr a2, ccompare2
#endif
esync
rsr a2, interrupt
wsr a2, intclear
@ -44,11 +88,12 @@ test rsil
assert eqi, a2, 0
test_end
#if L1_SOFT
test soft_disabled
set_vector kernel, 1f
clear_interrupts
movi a2, LSBIT(XCHAL_INTTYPE_MASK_SOFTWARE)
movi a2, L1_SOFT
wsr a2, intset
esync
rsr a3, interrupt
@ -70,7 +115,7 @@ test soft_intenable
set_vector kernel, 1f
clear_interrupts
movi a2, LSBIT(XCHAL_INTTYPE_MASK_SOFTWARE)
movi a2, L1_SOFT
wsr a2, intset
esync
rsr a3, interrupt
@ -89,7 +134,7 @@ test soft_rsil
set_vector kernel, 1f
clear_interrupts
movi a2, LSBIT(XCHAL_INTTYPE_MASK_SOFTWARE)
movi a2, L1_SOFT
wsr a2, intset
esync
rsr a3, interrupt
@ -108,7 +153,7 @@ test soft_waiti
set_vector kernel, 1f
clear_interrupts
movi a2, LSBIT(XCHAL_INTTYPE_MASK_SOFTWARE)
movi a2, L1_SOFT
wsr a2, intset
esync
rsr a3, interrupt
@ -127,7 +172,7 @@ test soft_user
set_vector user, 2f
clear_interrupts
movi a2, LSBIT(XCHAL_INTTYPE_MASK_SOFTWARE)
movi a2, L1_SOFT
wsr a2, intset
esync
rsr a3, interrupt
@ -147,12 +192,13 @@ test soft_user
check_l1
test_end
#if HIGH_LEVEL_SOFT
test soft_priority
set_vector kernel, 1f
set_vector level3, 2f
set_vector glue(level, HIGH_LEVEL_SOFT_LEVEL), 2f
clear_interrupts
movi a2, XCHAL_INTTYPE_MASK_SOFTWARE
movi a2, L1_SOFT | HIGH_LEVEL_SOFT
wsr a2, intenable
rsil a3, 0
esync
@ -164,17 +210,20 @@ test soft_priority
rsr a2, ps
movi a3, 0x1f /* EXCM | INTMASK */
and a2, a2, a3
movi a3, 0x13
movi a3, 0x10 | HIGH_LEVEL_SOFT_LEVEL
assert eq, a2, a3 /* EXCM and INTMASK are set
for high-priority interrupt */
test_end
#endif
#endif
#if HIGH_LEVEL_SOFT
test eps_epc_rfi
set_vector level3, 3f
set_vector glue(level, HIGH_LEVEL_SOFT_LEVEL), 3f
clear_interrupts
reset_ps
movi a2, XCHAL_INTTYPE_MASK_SOFTWARE
movi a2, L1_SOFT_MASK | HIGH_LEVEL_SOFT_MASK
wsr a2, intenable
rsil a3, 0
rsr a3, ps
@ -185,23 +234,26 @@ test eps_epc_rfi
2:
test_fail
3:
rsr a2, eps3
rsr a2, glue(eps, HIGH_LEVEL_SOFT_LEVEL)
assert eq, a2, a3
rsr a2, epc3
rsr a2, glue(epc, HIGH_LEVEL_SOFT_LEVEL)
movi a3, 1b
assert ge, a2, a3
movi a3, 2b
assert ge, a3, a2
movi a2, 4f
wsr a2, epc3
movi a2, 0x40003
wsr a2, eps3
rfi 3
wsr a2, glue(epc, HIGH_LEVEL_SOFT_LEVEL)
movi a2, 0x40000 | HIGH_LEVEL_SOFT_LEVEL
wsr a2, glue(eps, HIGH_LEVEL_SOFT_LEVEL)
rfi HIGH_LEVEL_SOFT_LEVEL
test_fail
4:
rsr a2, ps
movi a3, 0x40003
movi a3, 0x40000 | HIGH_LEVEL_SOFT_LEVEL
assert eq, a2, a3
test_end
#endif
#endif
test_suite_end

4
tests/tcg/xtensa/test_loop.S
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@ -2,6 +2,8 @@
test_suite loop
#if XCHAL_HAVE_LOOPS
test loop
movi a2, 0
movi a3, 5
@ -160,4 +162,6 @@ test loopgtz
1:
test_end
#endif
test_suite_end

122
tests/tcg/xtensa/test_lsc.S Normal file
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@ -0,0 +1,122 @@
#include "macros.inc"
test_suite lsc
#if XCHAL_HAVE_FP
test lsi
movi a2, 1
wsr a2, cpenable
movi a2, 1f
lsi f0, a2, 0
lsi f1, a2, 4
lsiu f2, a2, 8
movi a3, 1f + 8
assert eq, a2, a3
rfr a2, f0
movi a3, 0x3f800000
assert eq, a2, a3
rfr a2, f1
movi a3, 0x40000000
assert eq, a2, a3
rfr a2, f2
movi a3, 0x40400000
assert eq, a2, a3
.data
.align 4
1:
.float 1, 2, 3
.text
test_end
test ssi
movi a2, 1f
movi a3, 0x40800000
wfr f3, a3
ssi f3, a2, 0
movi a3, 0x40a00000
wfr f4, a3
ssi f4, a2, 4
movi a3, 0x40c00000
wfr f5, a3
ssiu f5, a2, 8
movi a3, 1f + 8
assert eq, a2, a3
l32i a4, a2, -8
movi a3, 0x40800000
assert eq, a4, a3
l32i a4, a2, -4
movi a3, 0x40a00000
assert eq, a4, a3
l32i a4, a2, 0
movi a3, 0x40c00000
assert eq, a4, a3
.data
.align 4
1:
.float 0, 0, 0
.text
test_end
test lsx
movi a2, 1f
movi a3, 0
lsx f6, a2, a3
movi a3, 4
lsx f7, a2, a3
movi a3, 8
lsxu f8, a2, a3
movi a3, 1f + 8
assert eq, a2, a3
rfr a2, f6
movi a3, 0x40e00000
assert eq, a2, a3
rfr a2, f7
movi a3, 0x41000000
assert eq, a2, a3
rfr a2, f8
movi a3, 0x41100000
assert eq, a2, a3
.data
.align 4
1:
.float 7, 8, 9
.text
test_end
test ssx
movi a2, 1f
movi a3, 0
movi a4, 0x41200000
wfr f9, a4
ssx f9, a2, a3
movi a3, 4
movi a4, 0x41300000
wfr f10, a4
ssx f10, a2, a3
movi a3, 8
movi a4, 0x41400000
wfr f11, a4
ssxu f11, a2, a3
movi a3, 1f + 8
assert eq, a2, a3
l32i a4, a2, -8
movi a3, 0x41200000
assert eq, a4, a3
l32i a4, a2, -4
movi a3, 0x41300000
assert eq, a4, a3
l32i a4, a2, 0
movi a3, 0x41400000
assert eq, a4, a3
.data
.align 4
1:
.float 0, 0, 0
.text
test_end
#endif
test_suite_end

4
tests/tcg/xtensa/test_mac16.S
View File

@ -2,6 +2,8 @@
test_suite mac16
#if XCHAL_HAVE_MAC16
#define ext16(v) (((v) & 0xffff) | (((v) & 0x8000) * 0x1ffffffe))
#define mul16(a, b) ((ext16(a) * ext16(b)))
@ -240,4 +242,6 @@ test mula_dd_lddec
.text
test_end
#endif
test_suite_end

4
tests/tcg/xtensa/test_max.S
View File

@ -2,6 +2,8 @@
test_suite max
#if XCHAL_HAVE_MINMAX
test max
movi a2, 0xffffffff
movi a3, 1
@ -78,4 +80,6 @@ test maxu
assert eq, a3, a4
test_end
#endif
test_suite_end

4
tests/tcg/xtensa/test_min.S
View File

@ -2,6 +2,8 @@
test_suite min
#if XCHAL_HAVE_MINMAX
test min
movi a2, 0xffffffff
movi a3, 1
@ -78,4 +80,6 @@ test minu
assert eq, a3, a4
test_end
#endif
test_suite_end

4
tests/tcg/xtensa/test_mmu.S
View File

@ -2,6 +2,8 @@
test_suite mmu
#if XCHAL_HAVE_PTP_MMU && !XCHAL_HAVE_SPANNING_WAY
.purgem test_init
.macro clean_tlb_way way, page_size, n_entries
@ -740,4 +742,6 @@ test cross_page_tb
assert eq, a2, a3
test_end
#endif
test_suite_end

4
tests/tcg/xtensa/test_mul16.S
View File

@ -2,6 +2,8 @@
test_suite mul16
#if XCHAL_HAVE_MUL16
test mul16u_pp
movi a2, 0x137f5a5a
mov a3, a2
@ -80,4 +82,6 @@ test mul16s_nn
assert eq, a3, a6
test_end
#endif
test_suite_end

4
tests/tcg/xtensa/test_mul32.S
View File

@ -2,6 +2,8 @@
test_suite mul32
#if XCHAL_HAVE_MUL32
test mull
movi a2, 0x137f5a5a
mov a3, a2
@ -15,6 +17,8 @@ test mull
assert eq, a3, a6
test_end
#endif
/* unfortunately dc232b doesn't have muluh/mulsh*/
test_suite_end

4
tests/tcg/xtensa/test_nsa.S
View File

@ -2,6 +2,8 @@
test_suite nsa
#if XCHAL_HAVE_NSA
test nsa
movi a2, 0
movi a3, 31
@ -56,4 +58,6 @@ test nsau
assert eq, a3, a2
test_end
#endif
test_suite_end

4
tests/tcg/xtensa/test_phys_mem.S
View File

@ -2,6 +2,8 @@
test_suite phys_mem
#if XCHAL_HAVE_PTP_MMU && !XCHAL_HAVE_SPANNING_WAY
.purgem test_init
.macro test_init
@ -67,6 +69,8 @@ test write_get_pte_no_phys
assert eq, a2, a3
test_end
#endif
test inst_fetch_no_phys
set_vector kernel, 2f

4
tests/tcg/xtensa/test_quo.S
View File

@ -2,6 +2,8 @@
test_suite quo
#if XCHAL_HAVE_DIV32
test quou_pp
movi a2, 0x5a5a137f
mov a3, a2
@ -144,4 +146,6 @@ test quos_exc
assert eq, a2, a3
test_end
#endif
test_suite_end

4
tests/tcg/xtensa/test_rem.S
View File

@ -2,6 +2,8 @@
test_suite rem
#if XCHAL_HAVE_DIV32
test remu_pp
movi a2, 0x5a5a137f
mov a3, a2
@ -144,4 +146,6 @@ test rems_exc
assert eq, a2, a3
test_end
#endif
test_suite_end

8
tests/tcg/xtensa/test_rst0.S
View File

@ -54,6 +54,8 @@ test add
assert eq, a4, a6
test_end
#if XCHAL_HAVE_ADDX
test addx2
movi a2, 0x137fa5a5
mov a3, a2
@ -93,6 +95,8 @@ test addx8
assert eq, a4, a6
test_end
#endif
test sub
movi a2, 0x137fa5a5
mov a3, a2
@ -106,6 +110,8 @@ test sub
assert eq, a4, a6
test_end
#if XCHAL_HAVE_ADDX
test subx2
movi a2, 0x137fa5a5
mov a3, a2
@ -145,4 +151,6 @@ test subx8
assert eq, a4, a6
test_end
#endif
test_suite_end

12
tests/tcg/xtensa/test_s32c1i.S
View File

@ -2,7 +2,13 @@
test_suite s32c1i
#if XCHAL_HAVE_S32C1I
test s32c1i_nowrite
#if XCHAL_HW_VERSION >= 230000
movi a2, 0x29
wsr a2, atomctl
#endif
movi a2, 1f
movi a3, 1
wsr a3, scompare1
@ -20,6 +26,10 @@ test s32c1i_nowrite
test_end
test s32c1i_write
#if XCHAL_HW_VERSION >= 230000
movi a2, 0x29
wsr a2, atomctl
#endif
movi a2, 1f
movi a3, 3
wsr a3, scompare1
@ -36,4 +46,6 @@ test s32c1i_write
.text
test_end
#endif
test_suite_end

4
tests/tcg/xtensa/test_sext.S
View File

@ -2,6 +2,8 @@
test_suite sext
#if XCHAL_HAVE_SEXT
test sext
movi a2, 0xffffff5a
movi a3, 0x0000005a
@ -66,4 +68,6 @@ test sext_same_rs
assert eq, a3, a2
test_end
#endif
test_suite_end

153
tests/tcg/xtensa/test_sr.S
View File

@ -2,11 +2,23 @@
test_suite sr
#if XCHAL_HAVE_BE
#define LOW__SR 0x04
#define HI_RSR 0x30
#define HI_WSR 0x31
#define HI_XSR 0x16
#else
#define LOW__SR 0x40
#define HI_RSR 0x03
#define HI_WSR 0x13
#define HI_XSR 0x61
#endif
.macro sr_op sym, op_sym, op_byte, sr
.if \sym
\op_sym a4, \sr
.else
.byte 0x40, \sr, \op_byte
.byte LOW__SR, \sr, \op_byte
.endif
.endm
@ -32,9 +44,9 @@ test_suite sr
.macro test_sr_mask sr, sym, mask
test \sr
test_sr_op \sym, \mask & 1, rsr, 0x03, \sr
test_sr_op \sym, \mask & 2, wsr, 0x13, \sr
test_sr_op \sym, \mask & 4, xsr, 0x61, \sr
test_sr_op \sym, \mask & 1, rsr, HI_RSR, \sr
test_sr_op \sym, \mask & 2, wsr, HI_WSR, \sr
test_sr_op \sym, \mask & 4, xsr, HI_XSR, \sr
test_end
.endm
@ -42,50 +54,183 @@ test_end
test_sr_mask \sr, \conf, 7
.endm
#if XCHAL_HAVE_MAC16
test_sr acchi, 1
test_sr acclo, 1
#else
test_sr_mask /*acchi*/17, 0, 0
test_sr_mask /*acclo*/16, 0, 0
#endif
#if XCHAL_HAVE_S32C1I && XCHAL_HW_VERSION >= 230000
test_sr atomctl, 1
#else
test_sr_mask /*atomctl*/99, 0, 0
#endif
#if XCHAL_HAVE_BOOLEANS
test_sr br, 1
#else
test_sr_mask /*br*/4, 0, 0
#endif
test_sr_mask /*cacheattr*/98, 0, 0
#if XCHAL_HAVE_CCOUNT
test_sr ccompare0, 1
test_sr ccount, 1
#else
test_sr_mask /*ccompare0*/240, 0, 0
test_sr_mask /*ccount*/234, 0, 0
#endif
#if XCHAL_HAVE_CP
test_sr cpenable, 1
#else
test_sr_mask /*cpenable*/224, 0, 0
#endif
#if XCHAL_HAVE_DEBUG
#if XCHAL_NUM_DBREAK
test_sr dbreaka0, 1
test_sr dbreakc0, 1
#endif
test_sr_mask debugcause, 1, 1
#else
test_sr_mask /*dbreaka0*/144, 0, 0
test_sr_mask /*dbreakc0*/160, 0, 0
test_sr_mask /*debugcause*/233, 0, 0
#endif
test_sr depc, 1
#if XCHAL_HAVE_PTP_MMU
test_sr dtlbcfg, 1
#else
test_sr_mask /*dtlbcfg*/92, 0, 0
#endif
test_sr epc1, 1
#if XCHAL_NUM_INTLEVELS > 1
test_sr epc2, 1
test_sr eps2, 1
#else
test_sr_mask /*epc2*/178, 0, 0
test_sr_mask /*eps2*/194, 0, 0
#endif
test_sr exccause, 1
test_sr excsave1, 1
#if XCHAL_NUM_INTLEVELS > 1
test_sr excsave2, 1
#else
test_sr_mask /*excsave2*/210, 0, 0
#endif
test_sr excvaddr, 1
#if XCHAL_HAVE_DEBUG
#if XCHAL_NUM_IBREAK
test_sr ibreaka0, 1
test_sr ibreakenable, 1
#endif
test_sr icount, 1
test_sr icountlevel, 1
#else
test_sr_mask /*ibreaka0*/128, 0, 0
test_sr_mask /*ibreakenable*/96, 0, 0
test_sr_mask /*icount*/236, 0, 0
test_sr_mask /*icountlevel*/237, 0, 0
#endif
test_sr_mask /*intclear*/227, 0, 2
test_sr_mask /*interrupt*/226, 0, 3
test_sr intenable, 1
#if XCHAL_HAVE_PTP_MMU
test_sr itlbcfg, 1
#else
test_sr_mask /*itlbcfg*/91, 0, 0
#endif
#if XCHAL_HAVE_LOOPS
test_sr lbeg, 1
test_sr lcount, 1
test_sr lend, 1
#else
test_sr_mask /*lbeg*/0, 0, 0
test_sr_mask /*lcount*/2, 0, 0
test_sr_mask /*lend*/1, 0, 0
#endif
#if XCHAL_HAVE_ABSOLUTE_LITERALS
test_sr litbase, 1
#else
test_sr_mask /*litbase*/5, 0, 0
#endif
#if XCHAL_HAVE_MAC16
test_sr m0, 1
#else
test_sr_mask /*m0*/32, 0, 0
#endif
#if XCHAL_HW_VERSION >= 250000
test_sr_mask /*memctl*/97, 0, 7
#else
test_sr_mask /*memctl*/97, 0, 0
#endif
#if XCHAL_NUM_MISC_REGS
test_sr misc0, 1
#else
test_sr_mask /*misc0*/244, 0, 0
#endif
#if XCHAL_HAVE_PREFETCH
test_sr prefctl, 1
#else
test_sr_mask /*prefctl*/40, 0, 0
#endif
#if XCHAL_HAVE_PRID
test_sr_mask /*prid*/235, 0, 1
#else
test_sr_mask /*prid*/235, 0, 0
#endif
test_sr ps, 1
#if XCHAL_HAVE_PTP_MMU
test_sr ptevaddr, 1
test_sr rasid, 1
#else
test_sr_mask /*ptevaddr*/83, 0, 0
test_sr_mask /*rasid*/90, 0, 0
#endif
test_sr sar, 1
#if XCHAL_HAVE_S32C1I
test_sr scompare1, 1
#else
test_sr_mask /*scompare1*/12, 0, 0
#endif
#if XCHAL_HAVE_VECBASE
test_sr vecbase, 1
#else
test_sr_mask /*vecbase*/231, 0, 0
#endif
#if XCHAL_HAVE_WINDOWED
test_sr windowbase, 1
test_sr windowstart, 1
#else
test_sr_mask /*windowbase*/72, 0, 0
test_sr_mask /*windowstart*/73, 0, 0
#endif
test_suite_end

48
tests/tcg/xtensa/test_timer.S
View File

@ -2,6 +2,8 @@
#define CCOUNT_SHIFT 4
#define WAIT_LOOPS 20
#define level1 kernel
#define INTERRUPT_LEVEL(n) glue3(XCHAL_INT, n, _LEVEL)
.macro make_ccount_delta target, delta
rsr \delta, ccount
@ -13,6 +15,8 @@
test_suite timer
#if XCHAL_HAVE_CCOUNT
test ccount
rsr a3, ccount
rsr a4, ccount
@ -32,14 +36,20 @@ test ccount_write
assert ltu, a3, a4
test_end
#if XCHAL_NUM_TIMERS
test ccount_update_deadline
movi a2, 0
wsr a2, intenable
rsr a2, interrupt
wsr a2, intclear
movi a2, 0
#if XCHAL_NUM_TIMERS > 1
wsr a2, ccompare1
#endif
#if XCHAL_NUM_TIMERS > 2
wsr a2, ccompare2
#endif
movi a2, 0x12345678
wsr a2, ccompare0
rsr a3, interrupt
@ -59,8 +69,12 @@ test ccompare
rsr a2, interrupt
wsr a2, intclear
movi a2, 0
#if XCHAL_NUM_TIMERS > 1
wsr a2, ccompare1
#endif
#if XCHAL_NUM_TIMERS > 2
wsr a2, ccompare2
#endif
make_ccount_delta a2, a15
wsr a2, ccompare0
@ -76,6 +90,7 @@ test ccompare
assert nei, a5, 0
test_end
#if INTERRUPT_LEVEL(XCHAL_TIMER0_INTERRUPT) == 1
test ccompare0_interrupt
set_vector kernel, 2f
movi a2, 0
@ -83,8 +98,12 @@ test ccompare0_interrupt
rsr a2, interrupt
wsr a2, intclear
movi a2, 0
#if XCHAL_NUM_TIMERS > 1
wsr a2, ccompare1
#endif
#if XCHAL_NUM_TIMERS > 2
wsr a2, ccompare2
#endif
movi a3, WAIT_LOOPS
make_ccount_delta a2, a15
@ -104,16 +123,21 @@ test ccompare0_interrupt
rsr a2, exccause
assert eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */
test_end
#endif
#if XCHAL_NUM_TIMERS > 1
test ccompare1_interrupt
set_vector level3, 2f
set_vector glue(level, INTERRUPT_LEVEL(XCHAL_TIMER1_INTERRUPT)), 2f
movi a2, 0
wsr a2, intenable
rsr a2, interrupt
wsr a2, intclear
movi a2, 0
wsr a2, ccompare0
#if XCHAL_NUM_TIMERS > 2
wsr a2, ccompare2
#endif
movi a3, WAIT_LOOPS
make_ccount_delta a2, a15
@ -123,7 +147,7 @@ test ccompare1_interrupt
assert eqi, a2, 0
movi a2, 1 << XCHAL_TIMER1_INTERRUPT
wsr a2, intenable
rsil a2, 2
rsil a2, INTERRUPT_LEVEL(XCHAL_TIMER1_INTERRUPT) - 1
loop a3, 1f
nop
1:
@ -131,8 +155,11 @@ test ccompare1_interrupt
2:
test_end
#endif
#if XCHAL_NUM_TIMERS > 2
test ccompare2_interrupt
set_vector level5, 2f
set_vector glue(level, INTERRUPT_LEVEL(XCHAL_TIMER2_INTERRUPT)), 2f
movi a2, 0
wsr a2, intenable
rsr a2, interrupt
@ -149,7 +176,7 @@ test ccompare2_interrupt
assert eqi, a2, 0
movi a2, 1 << XCHAL_TIMER2_INTERRUPT
wsr a2, intenable
rsil a2, 4
rsil a2, INTERRUPT_LEVEL(XCHAL_TIMER2_INTERRUPT) - 1
loop a3, 1f
nop
1:
@ -157,6 +184,8 @@ test ccompare2_interrupt
2:
test_end
#endif
test ccompare_interrupt_masked
set_vector kernel, 2f
movi a2, 0
@ -164,11 +193,15 @@ test ccompare_interrupt_masked
rsr a2, interrupt
wsr a2, intclear
movi a2, 0
#if XCHAL_NUM_TIMERS > 2
wsr a2, ccompare2
#endif
movi a3, 2 * WAIT_LOOPS
make_ccount_delta a2, a15
#if XCHAL_NUM_TIMERS > 1
wsr a2, ccompare1
#endif
add a2, a2, a15
wsr a2, ccompare0
rsync
@ -194,11 +227,15 @@ test ccompare_interrupt_masked_waiti
rsr a2, interrupt
wsr a2, intclear
movi a2, 0
#if XCHAL_NUM_TIMERS > 2
wsr a2, ccompare2
#endif
movi a3, 2 * WAIT_LOOPS
make_ccount_delta a2, a15
#if XCHAL_NUM_TIMERS > 1
wsr a2, ccompare1
#endif
add a2, a2, a15
wsr a2, ccompare0
rsync
@ -214,4 +251,7 @@ test ccompare_interrupt_masked_waiti
assert eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */
test_end
#endif
#endif
test_suite_end

32
tests/tcg/xtensa/test_windowed.S
View File

@ -2,10 +2,12 @@
test_suite windowed
#if XCHAL_HAVE_WINDOWED
.altmacro
.macro reset_window start
movi a2, 0xff
movi a2, 0xffff
wsr a2, windowstart
rsync
movi a2, 0
@ -105,7 +107,8 @@ test_end
movi a3, 0x4001f
assert eq, a2, a3
rsr a2, windowbase
assert eqi, a2, 8 - ((\window) / 4)
movi a3, (XCHAL_NUM_AREGS - (\window)) / 4
assert eq, a2, a3
rsr a2, windowstart
assert eqi, a2, 1
rfwu
@ -116,8 +119,8 @@ test_end
rsr a2, windowbase
assert eqi, a2, 0
rsr a2, windowstart
assert bsi, a2, 0
assert bsi, a2, 8 - ((\window) / 4)
assert bsi.l, a2, 0
assert bsi.l, a2, (XCHAL_NUM_AREGS - (\window)) / 4
.endm
test underflow
@ -132,7 +135,7 @@ test_end
.macro retw_test window
reset_window %(1 | (1 << (8 - (\window) / 4)))
reset_window %(1 | (1 << ((XCHAL_NUM_AREGS - \window) / 4)))
reset_ps
ssai 2
@ -147,10 +150,11 @@ test_end
movi a3, 0x4000f
assert eq, a2, a3
rsr a2, windowbase
assert eqi, a2, 8 - ((\window) / 4)
movi a3, (XCHAL_NUM_AREGS - (\window)) / 4
assert eq, a2, a3
rsr a2, windowstart
assert bci, a2, 0
assert bsi, a2, 8 - ((\window) / 4)
assert bci.l, a2, 0
assert bsi.l, a2, (XCHAL_NUM_AREGS - (\window)) / 4
.endm
test retw
@ -180,7 +184,7 @@ test movsp
set_vector kernel, 0
reset_window 0x81
reset_window %(0x1 | (1 << ((XCHAL_NUM_AREGS / 4) - 1)))
reset_ps
movsp a2, a3
@ -211,8 +215,16 @@ test rotw
movi a3, 0x16
movi a7, 0x17
#if XCHAL_NUM_AREGS == 32
movi a2, 0x44
wsr a2, windowstart
#elif XCHAL_NUM_AREGS == 64
movi a2, 0x4004
wsr a2, windowstart
rotw -8
#else
#error XCHAL_NUM_AREGS unsupported
#endif
rsync
movi a2, 0x10
@ -350,4 +362,6 @@ test entry_overflow
all_entry_overflow_tests
test_end
#endif
test_suite_end

14
tests/tcg/xtensa/vectors.S
View File

@ -2,10 +2,20 @@
.macro vector name
.section .vector.\name
.section .vector.\name, "ax"
.global vector_\name
vector_\name\():
j 1f
.section .vector.\name\().text
.literal_position
1:
wsr a0, excsave1
movi a0, 1f
ret.n
.section .vector.\name\().text, "ax"
.literal_position
1:
rsr a0, excsave1
wsr a2, excsave1
movi a2, handler_\name
l32i a2, a2, 0