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target/arm: Make MPU_MAIR0, MPU_MAIR1 registers banked for v8M 

Make the MPU registers MPU_MAIR0 and MPU_MAIR1 banked if v8M security
extensions are enabled.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1503414539-28762-13-git-send-email-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2017-09-07 13:54:53 +01:00
parent 45db7ba681
commit 4125e6feb7
4 changed files with 14 additions and 10 deletions
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8
hw/intc/armv7m_nvic.c
View File

@ -604,12 +604,12 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
goto bad_offset; goto bad_offset;
} }
return cpu->env.pmsav8.mair0; return cpu->env.pmsav8.mair0[attrs.secure];
case 0xdc4: /* MPU_MAIR1 */ case 0xdc4: /* MPU_MAIR1 */
if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
goto bad_offset; goto bad_offset;
} }
return cpu->env.pmsav8.mair1; return cpu->env.pmsav8.mair1[attrs.secure];
default: default:
bad_offset: bad_offset:
qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad read offset 0x%x\n", offset); qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad read offset 0x%x\n", offset);
@ -826,7 +826,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
} }
if (cpu->pmsav7_dregion) { if (cpu->pmsav7_dregion) {
/* Register is RES0 if no MPU regions are implemented */ /* Register is RES0 if no MPU regions are implemented */
cpu->env.pmsav8.mair0 = value; cpu->env.pmsav8.mair0[attrs.secure] = value;
} }
/* We don't need to do anything else because memory attributes /* We don't need to do anything else because memory attributes
* only affect cacheability, and we don't implement caching. * only affect cacheability, and we don't implement caching.
@ -838,7 +838,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
} }
if (cpu->pmsav7_dregion) { if (cpu->pmsav7_dregion) {
/* Register is RES0 if no MPU regions are implemented */ /* Register is RES0 if no MPU regions are implemented */
cpu->env.pmsav8.mair1 = value; cpu->env.pmsav8.mair1[attrs.secure] = value;
} }
/* We don't need to do anything else because memory attributes /* We don't need to do anything else because memory attributes
* only affect cacheability, and we don't implement caching. * only affect cacheability, and we don't implement caching.

6
target/arm/cpu.c
View File

@ -249,8 +249,10 @@ static void arm_cpu_reset(CPUState *s)
} }
} }
env->pmsav7.rnr = 0; env->pmsav7.rnr = 0;
env->pmsav8.mair0 = 0; env->pmsav8.mair0[M_REG_NS] = 0;
env->pmsav8.mair1 = 0; env->pmsav8.mair0[M_REG_S] = 0;
env->pmsav8.mair1[M_REG_NS] = 0;
env->pmsav8.mair1[M_REG_S] = 0;
} }
set_flush_to_zero(1, &env->vfp.standard_fp_status); set_flush_to_zero(1, &env->vfp.standard_fp_status);

4
target/arm/cpu.h
View File

@ -545,8 +545,8 @@ typedef struct CPUARMState {
*/ */
uint32_t *rbar; uint32_t *rbar;
uint32_t *rlar; uint32_t *rlar;
uint32_t mair0; uint32_t mair0[2];
uint32_t mair1; uint32_t mair1[2];
} pmsav8; } pmsav8;
void *nvic; void *nvic;

6
target/arm/machine.c
View File

@ -229,8 +229,8 @@ static const VMStateDescription vmstate_pmsav8 = {
vmstate_info_uint32, uint32_t), vmstate_info_uint32, uint32_t),
VMSTATE_VARRAY_UINT32(env.pmsav8.rlar, ARMCPU, pmsav7_dregion, 0, VMSTATE_VARRAY_UINT32(env.pmsav8.rlar, ARMCPU, pmsav7_dregion, 0,
vmstate_info_uint32, uint32_t), vmstate_info_uint32, uint32_t),
VMSTATE_UINT32(env.pmsav8.mair0, ARMCPU), VMSTATE_UINT32(env.pmsav8.mair0[M_REG_NS], ARMCPU),
VMSTATE_UINT32(env.pmsav8.mair1, ARMCPU), VMSTATE_UINT32(env.pmsav8.mair1[M_REG_NS], ARMCPU),
VMSTATE_END_OF_LIST() VMSTATE_END_OF_LIST()
} }
}; };
@ -255,6 +255,8 @@ static const VMStateDescription vmstate_m_security = {
VMSTATE_UINT32(env.v7m.faultmask[M_REG_S], ARMCPU), VMSTATE_UINT32(env.v7m.faultmask[M_REG_S], ARMCPU),
VMSTATE_UINT32(env.v7m.control[M_REG_S], ARMCPU), VMSTATE_UINT32(env.v7m.control[M_REG_S], ARMCPU),
VMSTATE_UINT32(env.v7m.vecbase[M_REG_S], ARMCPU), VMSTATE_UINT32(env.v7m.vecbase[M_REG_S], ARMCPU),
VMSTATE_UINT32(env.pmsav8.mair0[M_REG_S], ARMCPU),
VMSTATE_UINT32(env.pmsav8.mair1[M_REG_S], ARMCPU),
VMSTATE_END_OF_LIST() VMSTATE_END_OF_LIST()
} }
}; };