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target/sh4: Rename TCGv variables as manual for ADDV opcode 

To easily compare with the SH4 manual, rename:

  REG(B11_8) -> Rn
  REG(B7_4) -> Rm
  t0 -> result

Mention how overflow is calculated.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Message-Id: <20240430163125.77430-4-philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2024-04-30 16:43:05 +02:00
parent e88a856efd
commit 40ed073f89
1 changed files with 10 additions and 6 deletions
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16
target/sh4/translate.c
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@ -705,16 +705,20 @@ static void _decode_opc(DisasContext * ctx)
return;
case 0x300f: /* addv Rm,Rn */
{
TCGv t0, t1, t2;
t0 = tcg_temp_new();
tcg_gen_add_i32(t0, REG(B7_4), REG(B11_8));
TCGv Rn = REG(B11_8);
TCGv Rm = REG(B7_4);
TCGv result, t1, t2;
result = tcg_temp_new();
t1 = tcg_temp_new();
tcg_gen_xor_i32(t1, t0, REG(B11_8));
t2 = tcg_temp_new();
tcg_gen_xor_i32(t2, REG(B7_4), REG(B11_8));
tcg_gen_add_i32(result, Rm, Rn);
/* T = ((Rn ^ Rm) & (Result ^ Rn)) >> 31 */
tcg_gen_xor_i32(t1, result, Rn);
tcg_gen_xor_i32(t2, Rm, Rn);
tcg_gen_andc_i32(cpu_sr_t, t1, t2);
tcg_gen_shri_i32(cpu_sr_t, cpu_sr_t, 31);
tcg_gen_mov_i32(REG(B11_8), t0);
tcg_gen_mov_i32(Rn, result);
}
return;
case 0x2009: /* and Rm,Rn */