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target/riscv: rvv-1.0: set-X-first mask bit instructions 

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-32-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Frank Chang 2021-12-10 15:56:17 +08:00 committed by Alistair Francis
parent d71a24fc82
commit 40c1495d69
3 changed files with 7 additions and 8 deletions
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6
target/riscv/insn32.decode
View File

@ -629,9 +629,9 @@ vmornot_mm 011100 - ..... ..... 010 ..... 1010111 @r
vmxnor_mm 011111 - ..... ..... 010 ..... 1010111 @r vmxnor_mm 011111 - ..... ..... 010 ..... 1010111 @r
vcpop_m 010000 . ..... 10000 010 ..... 1010111 @r2_vm vcpop_m 010000 . ..... 10000 010 ..... 1010111 @r2_vm
vfirst_m 010000 . ..... 10001 010 ..... 1010111 @r2_vm vfirst_m 010000 . ..... 10001 010 ..... 1010111 @r2_vm
vmsbf_m 010110 . ..... 00001 010 ..... 1010111 @r2_vm vmsbf_m 010100 . ..... 00001 010 ..... 1010111 @r2_vm
vmsif_m 010110 . ..... 00011 010 ..... 1010111 @r2_vm vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm
vmsof_m 010110 . ..... 00010 010 ..... 1010111 @r2_vm vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm
viota_m 010110 . ..... 10000 010 ..... 1010111 @r2_vm viota_m 010110 . ..... 10000 010 ..... 1010111 @r2_vm
vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm
vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r

5
target/riscv/insn_trans/trans_rvv.c.inc
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@ -2731,7 +2731,10 @@ static bool trans_vfirst_m(DisasContext *s, arg_rmr *a)
#define GEN_M_TRANS(NAME) \ #define GEN_M_TRANS(NAME) \
static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
{ \ { \
if (vext_check_isa_ill(s)) { \ if (require_rvv(s) && \
vext_check_isa_ill(s) && \
require_vm(a->vm, a->rd) && \
(a->rd != a->rs2)) { \
uint32_t data = 0; \ uint32_t data = 0; \
gen_helper_gvec_3_ptr *fn = gen_helper_##NAME; \ gen_helper_gvec_3_ptr *fn = gen_helper_##NAME; \
TCGLabel *over = gen_new_label(); \ TCGLabel *over = gen_new_label(); \

4
target/riscv/vector_helper.c
View File

@ -4260,7 +4260,6 @@ enum set_mask_type {
static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env, static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env,
uint32_t desc, enum set_mask_type type) uint32_t desc, enum set_mask_type type)
{ {
uint32_t vlmax = env_archcpu(env)->cfg.vlen;
uint32_t vm = vext_vm(desc); uint32_t vm = vext_vm(desc);
uint32_t vl = env->vl; uint32_t vl = env->vl;
int i; int i;
@ -4290,9 +4289,6 @@ static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env,
} }
} }
} }
for (; i < vlmax; i++) {
vext_set_elem_mask(vd, i, 0);
}
} }
void HELPER(vmsbf_m)(void *vd, void *v0, void *vs2, CPURISCVState *env, void HELPER(vmsbf_m)(void *vd, void *v0, void *vs2, CPURISCVState *env,