mirror of https://github.com/xemu-project/xemu.git
target/arm: Split out get_phys_addr_twostage
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20221011031911.2408754-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
f3639a64f6
commit
3f5a74c543
191
target/arm/ptw.c
191
target/arm/ptw.c
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@ -31,6 +31,13 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
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GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
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__attribute__((nonnull));
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static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw,
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target_ulong address,
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MMUAccessType access_type,
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GetPhysAddrResult *result,
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ARMMMUFaultInfo *fi)
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__attribute__((nonnull));
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/* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. */
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static const uint8_t pamax_map[] = {
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[0] = 32,
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@ -2428,6 +2435,94 @@ static bool get_phys_addr_disabled(CPUARMState *env, target_ulong address,
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return 0;
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}
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static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw,
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target_ulong address,
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MMUAccessType access_type,
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GetPhysAddrResult *result,
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ARMMMUFaultInfo *fi)
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{
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hwaddr ipa;
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int s1_prot;
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int ret;
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bool is_secure = ptw->in_secure;
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bool ipa_secure, s2walk_secure;
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ARMCacheAttrs cacheattrs1;
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bool is_el0;
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uint64_t hcr;
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ret = get_phys_addr_with_struct(env, ptw, address, access_type, result, fi);
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/* If S1 fails or S2 is disabled, return early. */
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if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2, is_secure)) {
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return ret;
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}
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ipa = result->f.phys_addr;
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ipa_secure = result->f.attrs.secure;
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if (is_secure) {
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/* Select TCR based on the NS bit from the S1 walk. */
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s2walk_secure = !(ipa_secure
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? env->cp15.vstcr_el2 & VSTCR_SW
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: env->cp15.vtcr_el2 & VTCR_NSW);
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} else {
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assert(!ipa_secure);
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s2walk_secure = false;
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}
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is_el0 = ptw->in_mmu_idx == ARMMMUIdx_Stage1_E0;
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ptw->in_mmu_idx = s2walk_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2;
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ptw->in_secure = s2walk_secure;
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/*
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* S1 is done, now do S2 translation.
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* Save the stage1 results so that we may merge prot and cacheattrs later.
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*/
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s1_prot = result->f.prot;
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cacheattrs1 = result->cacheattrs;
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memset(result, 0, sizeof(*result));
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ret = get_phys_addr_lpae(env, ptw, ipa, access_type, is_el0, result, fi);
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fi->s2addr = ipa;
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/* Combine the S1 and S2 perms. */
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result->f.prot &= s1_prot;
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/* If S2 fails, return early. */
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if (ret) {
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return ret;
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}
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/* Combine the S1 and S2 cache attributes. */
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hcr = arm_hcr_el2_eff_secstate(env, is_secure);
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if (hcr & HCR_DC) {
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/*
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* HCR.DC forces the first stage attributes to
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* Normal Non-Shareable,
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* Inner Write-Back Read-Allocate Write-Allocate,
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* Outer Write-Back Read-Allocate Write-Allocate.
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* Do not overwrite Tagged within attrs.
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*/
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if (cacheattrs1.attrs != 0xf0) {
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cacheattrs1.attrs = 0xff;
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}
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cacheattrs1.shareability = 0;
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}
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result->cacheattrs = combine_cacheattrs(hcr, cacheattrs1,
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result->cacheattrs);
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/*
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* Check if IPA translates to secure or non-secure PA space.
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* Note that VSTCR overrides VTCR and {N}SW overrides {N}SA.
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*/
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result->f.attrs.secure =
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(is_secure
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&& !(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW))
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&& (ipa_secure
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|| !(env->cp15.vtcr_el2 & (VTCR_NSA | VTCR_NSW))));
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return 0;
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}
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static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw,
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target_ulong address,
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MMUAccessType access_type,
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@ -2441,99 +2536,13 @@ static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw,
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if (mmu_idx != s1_mmu_idx) {
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/*
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* Call ourselves recursively to do the stage 1 and then stage 2
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* translations if mmu_idx is a two-stage regime.
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* translations if mmu_idx is a two-stage regime, and EL2 present.
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* Otherwise, a stage1+stage2 translation is just stage 1.
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*/
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ptw->in_mmu_idx = mmu_idx = s1_mmu_idx;
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if (arm_feature(env, ARM_FEATURE_EL2)) {
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hwaddr ipa;
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int s1_prot;
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int ret;
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bool ipa_secure, s2walk_secure;
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ARMCacheAttrs cacheattrs1;
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bool is_el0;
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uint64_t hcr;
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ptw->in_mmu_idx = s1_mmu_idx;
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ret = get_phys_addr_with_struct(env, ptw, address, access_type,
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result, fi);
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/* If S1 fails or S2 is disabled, return early. */
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if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2,
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is_secure)) {
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return ret;
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}
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ipa = result->f.phys_addr;
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ipa_secure = result->f.attrs.secure;
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if (is_secure) {
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/* Select TCR based on the NS bit from the S1 walk. */
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s2walk_secure = !(ipa_secure
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? env->cp15.vstcr_el2 & VSTCR_SW
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: env->cp15.vtcr_el2 & VTCR_NSW);
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} else {
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assert(!ipa_secure);
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s2walk_secure = false;
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}
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ptw->in_mmu_idx =
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s2walk_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2;
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ptw->in_secure = s2walk_secure;
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is_el0 = mmu_idx == ARMMMUIdx_E10_0;
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/*
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* S1 is done, now do S2 translation.
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* Save the stage1 results so that we may merge
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* prot and cacheattrs later.
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*/
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s1_prot = result->f.prot;
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cacheattrs1 = result->cacheattrs;
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memset(result, 0, sizeof(*result));
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ret = get_phys_addr_lpae(env, ptw, ipa, access_type,
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is_el0, result, fi);
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fi->s2addr = ipa;
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/* Combine the S1 and S2 perms. */
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result->f.prot &= s1_prot;
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/* If S2 fails, return early. */
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if (ret) {
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return ret;
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}
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/* Combine the S1 and S2 cache attributes. */
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hcr = arm_hcr_el2_eff_secstate(env, is_secure);
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if (hcr & HCR_DC) {
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/*
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* HCR.DC forces the first stage attributes to
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* Normal Non-Shareable,
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* Inner Write-Back Read-Allocate Write-Allocate,
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* Outer Write-Back Read-Allocate Write-Allocate.
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* Do not overwrite Tagged within attrs.
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*/
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if (cacheattrs1.attrs != 0xf0) {
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cacheattrs1.attrs = 0xff;
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}
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cacheattrs1.shareability = 0;
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}
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result->cacheattrs = combine_cacheattrs(hcr, cacheattrs1,
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result->cacheattrs);
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/*
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* Check if IPA translates to secure or non-secure PA space.
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* Note that VSTCR overrides VTCR and {N}SW overrides {N}SA.
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*/
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result->f.attrs.secure =
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(is_secure
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&& !(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW))
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&& (ipa_secure
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|| !(env->cp15.vtcr_el2 & (VTCR_NSA | VTCR_NSW))));
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return 0;
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} else {
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/*
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* For non-EL2 CPUs a stage1+stage2 translation is just stage 1.
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*/
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mmu_idx = stage_1_mmu_idx(mmu_idx);
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return get_phys_addr_twostage(env, ptw, address, access_type,
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result, fi);
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}
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}
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