mirror of https://github.com/xemu-project/xemu.git
target/loongarch: Implement xvmadd/xvmsub/xvmaddw{ev/od}
This patch includes:
- XVMADD.{B/H/W/D};
- XVMSUB.{B/H/W/D};
- XVMADDW{EV/OD}.{H.B/W.H/D.W/Q.D}[U];
- XVMADDW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230914022645.1151356-27-gaosong@loongson.cn>
This commit is contained in:
Song Gao
parent
342dc1cfcb
commit
3f450c17d0
|
|
@ -1928,6 +1928,40 @@ INSN_LASX(xvmulwod_w_hu_h, vvv)
|
|||
INSN_LASX(xvmulwod_d_wu_w, vvv)
|
||||
INSN_LASX(xvmulwod_q_du_d, vvv)
|
||||
|
||||
INSN_LASX(xvmadd_b, vvv)
|
||||
INSN_LASX(xvmadd_h, vvv)
|
||||
INSN_LASX(xvmadd_w, vvv)
|
||||
INSN_LASX(xvmadd_d, vvv)
|
||||
INSN_LASX(xvmsub_b, vvv)
|
||||
INSN_LASX(xvmsub_h, vvv)
|
||||
INSN_LASX(xvmsub_w, vvv)
|
||||
INSN_LASX(xvmsub_d, vvv)
|
||||
|
||||
INSN_LASX(xvmaddwev_h_b, vvv)
|
||||
INSN_LASX(xvmaddwev_w_h, vvv)
|
||||
INSN_LASX(xvmaddwev_d_w, vvv)
|
||||
INSN_LASX(xvmaddwev_q_d, vvv)
|
||||
INSN_LASX(xvmaddwod_h_b, vvv)
|
||||
INSN_LASX(xvmaddwod_w_h, vvv)
|
||||
INSN_LASX(xvmaddwod_d_w, vvv)
|
||||
INSN_LASX(xvmaddwod_q_d, vvv)
|
||||
INSN_LASX(xvmaddwev_h_bu, vvv)
|
||||
INSN_LASX(xvmaddwev_w_hu, vvv)
|
||||
INSN_LASX(xvmaddwev_d_wu, vvv)
|
||||
INSN_LASX(xvmaddwev_q_du, vvv)
|
||||
INSN_LASX(xvmaddwod_h_bu, vvv)
|
||||
INSN_LASX(xvmaddwod_w_hu, vvv)
|
||||
INSN_LASX(xvmaddwod_d_wu, vvv)
|
||||
INSN_LASX(xvmaddwod_q_du, vvv)
|
||||
INSN_LASX(xvmaddwev_h_bu_b, vvv)
|
||||
INSN_LASX(xvmaddwev_w_hu_h, vvv)
|
||||
INSN_LASX(xvmaddwev_d_wu_w, vvv)
|
||||
INSN_LASX(xvmaddwev_q_du_d, vvv)
|
||||
INSN_LASX(xvmaddwod_h_bu_b, vvv)
|
||||
INSN_LASX(xvmaddwod_w_hu_h, vvv)
|
||||
INSN_LASX(xvmaddwod_d_wu_w, vvv)
|
||||
INSN_LASX(xvmaddwod_q_du_d, vvv)
|
||||
|
||||
INSN_LASX(xvreplgr2vr_b, vr)
|
||||
INSN_LASX(xvreplgr2vr_h, vr)
|
||||
INSN_LASX(xvreplgr2vr_w, vr)
|
||||
|
|
|
|||
|
|
@ -2591,6 +2591,10 @@ TRANS(vmadd_b, LSX, gvec_vvv, MO_8, do_vmadd)
|
|||
TRANS(vmadd_h, LSX, gvec_vvv, MO_16, do_vmadd)
|
||||
TRANS(vmadd_w, LSX, gvec_vvv, MO_32, do_vmadd)
|
||||
TRANS(vmadd_d, LSX, gvec_vvv, MO_64, do_vmadd)
|
||||
TRANS(xvmadd_b, LASX, gvec_xxx, MO_8, do_vmadd)
|
||||
TRANS(xvmadd_h, LASX, gvec_xxx, MO_16, do_vmadd)
|
||||
TRANS(xvmadd_w, LASX, gvec_xxx, MO_32, do_vmadd)
|
||||
TRANS(xvmadd_d, LASX, gvec_xxx, MO_64, do_vmadd)
|
||||
|
||||
static void gen_vmsub(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
|
||||
{
|
||||
|
|
@ -2665,6 +2669,10 @@ TRANS(vmsub_b, LSX, gvec_vvv, MO_8, do_vmsub)
|
|||
TRANS(vmsub_h, LSX, gvec_vvv, MO_16, do_vmsub)
|
||||
TRANS(vmsub_w, LSX, gvec_vvv, MO_32, do_vmsub)
|
||||
TRANS(vmsub_d, LSX, gvec_vvv, MO_64, do_vmsub)
|
||||
TRANS(xvmsub_b, LASX, gvec_xxx, MO_8, do_vmsub)
|
||||
TRANS(xvmsub_h, LASX, gvec_xxx, MO_16, do_vmsub)
|
||||
TRANS(xvmsub_w, LASX, gvec_xxx, MO_32, do_vmsub)
|
||||
TRANS(xvmsub_d, LASX, gvec_xxx, MO_64, do_vmsub)
|
||||
|
||||
static void gen_vmaddwev_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
|
||||
{
|
||||
|
|
@ -2739,43 +2747,69 @@ static void do_vmaddwev_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
|
|||
TRANS(vmaddwev_h_b, LSX, gvec_vvv, MO_8, do_vmaddwev_s)
|
||||
TRANS(vmaddwev_w_h, LSX, gvec_vvv, MO_16, do_vmaddwev_s)
|
||||
TRANS(vmaddwev_d_w, LSX, gvec_vvv, MO_32, do_vmaddwev_s)
|
||||
TRANS(xvmaddwev_h_b, LASX, gvec_xxx, MO_8, do_vmaddwev_s)
|
||||
TRANS(xvmaddwev_w_h, LASX, gvec_xxx, MO_16, do_vmaddwev_s)
|
||||
TRANS(xvmaddwev_d_w, LASX, gvec_xxx, MO_32, do_vmaddwev_s)
|
||||
|
||||
#define VMADD_Q(NAME, FN, idx1, idx2) \
|
||||
static bool trans_## NAME (DisasContext *ctx, arg_vvv *a) \
|
||||
{ \
|
||||
TCGv_i64 rh, rl, arg1, arg2, th, tl; \
|
||||
\
|
||||
if (!avail_LSX(ctx)) { \
|
||||
return false; \
|
||||
} \
|
||||
\
|
||||
rh = tcg_temp_new_i64(); \
|
||||
rl = tcg_temp_new_i64(); \
|
||||
arg1 = tcg_temp_new_i64(); \
|
||||
arg2 = tcg_temp_new_i64(); \
|
||||
th = tcg_temp_new_i64(); \
|
||||
tl = tcg_temp_new_i64(); \
|
||||
\
|
||||
get_vreg64(arg1, a->vj, idx1); \
|
||||
get_vreg64(arg2, a->vk, idx2); \
|
||||
get_vreg64(rh, a->vd, 1); \
|
||||
get_vreg64(rl, a->vd, 0); \
|
||||
\
|
||||
tcg_gen_## FN ##_i64(tl, th, arg1, arg2); \
|
||||
tcg_gen_add2_i64(rl, rh, rl, rh, tl, th); \
|
||||
\
|
||||
set_vreg64(rh, a->vd, 1); \
|
||||
set_vreg64(rl, a->vd, 0); \
|
||||
\
|
||||
return true; \
|
||||
static bool gen_vmadd_q_vl(DisasContext * ctx,
|
||||
arg_vvv *a, uint32_t oprsz, int idx1, int idx2,
|
||||
void (*func)(TCGv_i64, TCGv_i64,
|
||||
TCGv_i64, TCGv_i64))
|
||||
{
|
||||
TCGv_i64 rh, rl, arg1, arg2, th, tl;
|
||||
int i;
|
||||
|
||||
if (!check_vec(ctx, oprsz)) {
|
||||
return true;
|
||||
}
|
||||
|
||||
rh = tcg_temp_new_i64();
|
||||
rl = tcg_temp_new_i64();
|
||||
arg1 = tcg_temp_new_i64();
|
||||
arg2 = tcg_temp_new_i64();
|
||||
th = tcg_temp_new_i64();
|
||||
tl = tcg_temp_new_i64();
|
||||
|
||||
for (i = 0; i < oprsz / 16; i++) {
|
||||
get_vreg64(arg1, a->vj, 2 * i + idx1);
|
||||
get_vreg64(arg2, a->vk, 2 * i + idx2);
|
||||
get_vreg64(rh, a->vd, 2 * i + 1);
|
||||
get_vreg64(rl, a->vd, 2 * i);
|
||||
|
||||
func(tl, th, arg1, arg2);
|
||||
tcg_gen_add2_i64(rl, rh, rl, rh, tl, th);
|
||||
|
||||
set_vreg64(rh, a->vd, 2 * i + 1);
|
||||
set_vreg64(rl, a->vd, 2 * i);
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
VMADD_Q(vmaddwev_q_d, muls2, 0, 0)
|
||||
VMADD_Q(vmaddwod_q_d, muls2, 1, 1)
|
||||
VMADD_Q(vmaddwev_q_du, mulu2, 0, 0)
|
||||
VMADD_Q(vmaddwod_q_du, mulu2, 1, 1)
|
||||
VMADD_Q(vmaddwev_q_du_d, mulus2, 0, 0)
|
||||
VMADD_Q(vmaddwod_q_du_d, mulus2, 1, 1)
|
||||
static bool gen_vmadd_q(DisasContext *ctx, arg_vvv *a, int idx1, int idx2,
|
||||
void (*func)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
|
||||
{
|
||||
return gen_vmadd_q_vl(ctx, a, 16, idx1, idx2, func);
|
||||
}
|
||||
|
||||
static bool gen_xvmadd_q(DisasContext *ctx, arg_vvv *a, int idx1, int idx2,
|
||||
void (*func)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
|
||||
{
|
||||
return gen_vmadd_q_vl(ctx, a, 32, idx1, idx2, func);
|
||||
}
|
||||
|
||||
TRANS(vmaddwev_q_d, LSX, gen_vmadd_q, 0, 0, tcg_gen_muls2_i64)
|
||||
TRANS(vmaddwod_q_d, LSX, gen_vmadd_q, 1, 1, tcg_gen_muls2_i64)
|
||||
TRANS(vmaddwev_q_du, LSX, gen_vmadd_q, 0, 0, tcg_gen_mulu2_i64)
|
||||
TRANS(vmaddwod_q_du, LSX, gen_vmadd_q, 1, 1, tcg_gen_mulu2_i64)
|
||||
TRANS(vmaddwev_q_du_d, LSX, gen_vmadd_q, 0, 0, tcg_gen_mulus2_i64)
|
||||
TRANS(vmaddwod_q_du_d, LSX, gen_vmadd_q, 1, 1, tcg_gen_mulus2_i64)
|
||||
TRANS(xvmaddwev_q_d, LASX, gen_xvmadd_q, 0, 0, tcg_gen_muls2_i64)
|
||||
TRANS(xvmaddwod_q_d, LASX, gen_xvmadd_q, 1, 1, tcg_gen_muls2_i64)
|
||||
TRANS(xvmaddwev_q_du, LASX, gen_xvmadd_q, 0, 0, tcg_gen_mulu2_i64)
|
||||
TRANS(xvmaddwod_q_du, LASX, gen_xvmadd_q, 1, 1, tcg_gen_mulu2_i64)
|
||||
TRANS(xvmaddwev_q_du_d, LASX, gen_xvmadd_q, 0, 0, tcg_gen_mulus2_i64)
|
||||
TRANS(xvmaddwod_q_du_d, LASX, gen_xvmadd_q, 1, 1, tcg_gen_mulus2_i64)
|
||||
|
||||
static void gen_vmaddwod_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
|
||||
{
|
||||
|
|
@ -2847,6 +2881,9 @@ static void do_vmaddwod_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
|
|||
TRANS(vmaddwod_h_b, LSX, gvec_vvv, MO_8, do_vmaddwod_s)
|
||||
TRANS(vmaddwod_w_h, LSX, gvec_vvv, MO_16, do_vmaddwod_s)
|
||||
TRANS(vmaddwod_d_w, LSX, gvec_vvv, MO_32, do_vmaddwod_s)
|
||||
TRANS(xvmaddwod_h_b, LASX, gvec_xxx, MO_8, do_vmaddwod_s)
|
||||
TRANS(xvmaddwod_w_h, LASX, gvec_xxx, MO_16, do_vmaddwod_s)
|
||||
TRANS(xvmaddwod_d_w, LASX, gvec_xxx, MO_32, do_vmaddwod_s)
|
||||
|
||||
static void gen_vmaddwev_u(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
|
||||
{
|
||||
|
|
@ -2917,6 +2954,9 @@ static void do_vmaddwev_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
|
|||
TRANS(vmaddwev_h_bu, LSX, gvec_vvv, MO_8, do_vmaddwev_u)
|
||||
TRANS(vmaddwev_w_hu, LSX, gvec_vvv, MO_16, do_vmaddwev_u)
|
||||
TRANS(vmaddwev_d_wu, LSX, gvec_vvv, MO_32, do_vmaddwev_u)
|
||||
TRANS(xvmaddwev_h_bu, LASX, gvec_xxx, MO_8, do_vmaddwev_u)
|
||||
TRANS(xvmaddwev_w_hu, LASX, gvec_xxx, MO_16, do_vmaddwev_u)
|
||||
TRANS(xvmaddwev_d_wu, LASX, gvec_xxx, MO_32, do_vmaddwev_u)
|
||||
|
||||
static void gen_vmaddwod_u(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
|
||||
{
|
||||
|
|
@ -2988,6 +3028,9 @@ static void do_vmaddwod_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
|
|||
TRANS(vmaddwod_h_bu, LSX, gvec_vvv, MO_8, do_vmaddwod_u)
|
||||
TRANS(vmaddwod_w_hu, LSX, gvec_vvv, MO_16, do_vmaddwod_u)
|
||||
TRANS(vmaddwod_d_wu, LSX, gvec_vvv, MO_32, do_vmaddwod_u)
|
||||
TRANS(xvmaddwod_h_bu, LASX, gvec_xxx, MO_8, do_vmaddwod_u)
|
||||
TRANS(xvmaddwod_w_hu, LASX, gvec_xxx, MO_16, do_vmaddwod_u)
|
||||
TRANS(xvmaddwod_d_wu, LASX, gvec_xxx, MO_32, do_vmaddwod_u)
|
||||
|
||||
static void gen_vmaddwev_u_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
|
||||
{
|
||||
|
|
@ -3061,6 +3104,9 @@ static void do_vmaddwev_u_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
|
|||
TRANS(vmaddwev_h_bu_b, LSX, gvec_vvv, MO_8, do_vmaddwev_u_s)
|
||||
TRANS(vmaddwev_w_hu_h, LSX, gvec_vvv, MO_16, do_vmaddwev_u_s)
|
||||
TRANS(vmaddwev_d_wu_w, LSX, gvec_vvv, MO_32, do_vmaddwev_u_s)
|
||||
TRANS(xvmaddwev_h_bu_b, LASX, gvec_xxx, MO_8, do_vmaddwev_u_s)
|
||||
TRANS(xvmaddwev_w_hu_h, LASX, gvec_xxx, MO_16, do_vmaddwev_u_s)
|
||||
TRANS(xvmaddwev_d_wu_w, LASX, gvec_xxx, MO_32, do_vmaddwev_u_s)
|
||||
|
||||
static void gen_vmaddwod_u_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
|
||||
{
|
||||
|
|
@ -3133,6 +3179,9 @@ static void do_vmaddwod_u_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
|
|||
TRANS(vmaddwod_h_bu_b, LSX, gvec_vvv, MO_8, do_vmaddwod_u_s)
|
||||
TRANS(vmaddwod_w_hu_h, LSX, gvec_vvv, MO_16, do_vmaddwod_u_s)
|
||||
TRANS(vmaddwod_d_wu_w, LSX, gvec_vvv, MO_32, do_vmaddwod_u_s)
|
||||
TRANS(xvmaddwod_h_bu_b, LASX, gvec_xxx, MO_8, do_vmaddwod_u_s)
|
||||
TRANS(xvmaddwod_w_hu_h, LASX, gvec_xxx, MO_16, do_vmaddwod_u_s)
|
||||
TRANS(xvmaddwod_d_wu_w, LASX, gvec_xxx, MO_32, do_vmaddwod_u_s)
|
||||
|
||||
TRANS(vdiv_b, LSX, gen_vvv, gen_helper_vdiv_b)
|
||||
TRANS(vdiv_h, LSX, gen_vvv, gen_helper_vdiv_h)
|
||||
|
|
|
|||
|
|
@ -1511,6 +1511,40 @@ xvmulwod_w_hu_h 0111 01001010 00101 ..... ..... ..... @vvv
|
|||
xvmulwod_d_wu_w 0111 01001010 00110 ..... ..... ..... @vvv
|
||||
xvmulwod_q_du_d 0111 01001010 00111 ..... ..... ..... @vvv
|
||||
|
||||
xvmadd_b 0111 01001010 10000 ..... ..... ..... @vvv
|
||||
xvmadd_h 0111 01001010 10001 ..... ..... ..... @vvv
|
||||
xvmadd_w 0111 01001010 10010 ..... ..... ..... @vvv
|
||||
xvmadd_d 0111 01001010 10011 ..... ..... ..... @vvv
|
||||
xvmsub_b 0111 01001010 10100 ..... ..... ..... @vvv
|
||||
xvmsub_h 0111 01001010 10101 ..... ..... ..... @vvv
|
||||
xvmsub_w 0111 01001010 10110 ..... ..... ..... @vvv
|
||||
xvmsub_d 0111 01001010 10111 ..... ..... ..... @vvv
|
||||
|
||||
xvmaddwev_h_b 0111 01001010 11000 ..... ..... ..... @vvv
|
||||
xvmaddwev_w_h 0111 01001010 11001 ..... ..... ..... @vvv
|
||||
xvmaddwev_d_w 0111 01001010 11010 ..... ..... ..... @vvv
|
||||
xvmaddwev_q_d 0111 01001010 11011 ..... ..... ..... @vvv
|
||||
xvmaddwod_h_b 0111 01001010 11100 ..... ..... ..... @vvv
|
||||
xvmaddwod_w_h 0111 01001010 11101 ..... ..... ..... @vvv
|
||||
xvmaddwod_d_w 0111 01001010 11110 ..... ..... ..... @vvv
|
||||
xvmaddwod_q_d 0111 01001010 11111 ..... ..... ..... @vvv
|
||||
xvmaddwev_h_bu 0111 01001011 01000 ..... ..... ..... @vvv
|
||||
xvmaddwev_w_hu 0111 01001011 01001 ..... ..... ..... @vvv
|
||||
xvmaddwev_d_wu 0111 01001011 01010 ..... ..... ..... @vvv
|
||||
xvmaddwev_q_du 0111 01001011 01011 ..... ..... ..... @vvv
|
||||
xvmaddwod_h_bu 0111 01001011 01100 ..... ..... ..... @vvv
|
||||
xvmaddwod_w_hu 0111 01001011 01101 ..... ..... ..... @vvv
|
||||
xvmaddwod_d_wu 0111 01001011 01110 ..... ..... ..... @vvv
|
||||
xvmaddwod_q_du 0111 01001011 01111 ..... ..... ..... @vvv
|
||||
xvmaddwev_h_bu_b 0111 01001011 11000 ..... ..... ..... @vvv
|
||||
xvmaddwev_w_hu_h 0111 01001011 11001 ..... ..... ..... @vvv
|
||||
xvmaddwev_d_wu_w 0111 01001011 11010 ..... ..... ..... @vvv
|
||||
xvmaddwev_q_du_d 0111 01001011 11011 ..... ..... ..... @vvv
|
||||
xvmaddwod_h_bu_b 0111 01001011 11100 ..... ..... ..... @vvv
|
||||
xvmaddwod_w_hu_h 0111 01001011 11101 ..... ..... ..... @vvv
|
||||
xvmaddwod_d_wu_w 0111 01001011 11110 ..... ..... ..... @vvv
|
||||
xvmaddwod_q_du_d 0111 01001011 11111 ..... ..... ..... @vvv
|
||||
|
||||
xvreplgr2vr_b 0111 01101001 11110 00000 ..... ..... @vr
|
||||
xvreplgr2vr_h 0111 01101001 11110 00001 ..... ..... @vr
|
||||
xvreplgr2vr_w 0111 01101001 11110 00010 ..... ..... @vr
|
||||
|
|
|
|||
|
|
@ -529,16 +529,18 @@ DO_ODD_U_S(vmulwod_d_wu_w, 64, D, UD, W, UW, DO_MUL)
|
|||
#define DO_MADD(a, b, c) (a + b * c)
|
||||
#define DO_MSUB(a, b, c) (a - b * c)
|
||||
|
||||
#define VMADDSUB(NAME, BIT, E, DO_OP) \
|
||||
void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t v) \
|
||||
{ \
|
||||
int i; \
|
||||
VReg *Vd = (VReg *)vd; \
|
||||
VReg *Vj = (VReg *)vj; \
|
||||
VReg *Vk = (VReg *)vk; \
|
||||
for (i = 0; i < LSX_LEN/BIT; i++) { \
|
||||
Vd->E(i) = DO_OP(Vd->E(i), Vj->E(i) ,Vk->E(i)); \
|
||||
} \
|
||||
#define VMADDSUB(NAME, BIT, E, DO_OP) \
|
||||
void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
|
||||
{ \
|
||||
int i; \
|
||||
VReg *Vd = (VReg *)vd; \
|
||||
VReg *Vj = (VReg *)vj; \
|
||||
VReg *Vk = (VReg *)vk; \
|
||||
int oprsz = simd_oprsz(desc); \
|
||||
\
|
||||
for (i = 0; i < oprsz / (BIT / 8); i++) { \
|
||||
Vd->E(i) = DO_OP(Vd->E(i), Vj->E(i) ,Vk->E(i)); \
|
||||
} \
|
||||
}
|
||||
|
||||
VMADDSUB(vmadd_b, 8, B, DO_MADD)
|
||||
|
|
@ -551,15 +553,16 @@ VMADDSUB(vmsub_w, 32, W, DO_MSUB)
|
|||
VMADDSUB(vmsub_d, 64, D, DO_MSUB)
|
||||
|
||||
#define VMADDWEV(NAME, BIT, E1, E2, DO_OP) \
|
||||
void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t v) \
|
||||
void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
|
||||
{ \
|
||||
int i; \
|
||||
VReg *Vd = (VReg *)vd; \
|
||||
VReg *Vj = (VReg *)vj; \
|
||||
VReg *Vk = (VReg *)vk; \
|
||||
typedef __typeof(Vd->E1(0)) TD; \
|
||||
int oprsz = simd_oprsz(desc); \
|
||||
\
|
||||
for (i = 0; i < LSX_LEN/BIT; i++) { \
|
||||
for (i = 0; i < oprsz / (BIT / 8); i++) { \
|
||||
Vd->E1(i) += DO_OP((TD)Vj->E2(2 * i), (TD)Vk->E2(2 * i)); \
|
||||
} \
|
||||
}
|
||||
|
|
@ -571,19 +574,20 @@ VMADDWEV(vmaddwev_h_bu, 16, UH, UB, DO_MUL)
|
|||
VMADDWEV(vmaddwev_w_hu, 32, UW, UH, DO_MUL)
|
||||
VMADDWEV(vmaddwev_d_wu, 64, UD, UW, DO_MUL)
|
||||
|
||||
#define VMADDWOD(NAME, BIT, E1, E2, DO_OP) \
|
||||
void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t v) \
|
||||
{ \
|
||||
int i; \
|
||||
VReg *Vd = (VReg *)vd; \
|
||||
VReg *Vj = (VReg *)vj; \
|
||||
VReg *Vk = (VReg *)vk; \
|
||||
typedef __typeof(Vd->E1(0)) TD; \
|
||||
\
|
||||
for (i = 0; i < LSX_LEN/BIT; i++) { \
|
||||
Vd->E1(i) += DO_OP((TD)Vj->E2(2 * i + 1), \
|
||||
(TD)Vk->E2(2 * i + 1)); \
|
||||
} \
|
||||
#define VMADDWOD(NAME, BIT, E1, E2, DO_OP) \
|
||||
void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
|
||||
{ \
|
||||
int i; \
|
||||
VReg *Vd = (VReg *)vd; \
|
||||
VReg *Vj = (VReg *)vj; \
|
||||
VReg *Vk = (VReg *)vk; \
|
||||
typedef __typeof(Vd->E1(0)) TD; \
|
||||
int oprsz = simd_oprsz(desc); \
|
||||
\
|
||||
for (i = 0; i < oprsz / (BIT / 8); i++) { \
|
||||
Vd->E1(i) += DO_OP((TD)Vj->E2(2 * i + 1), \
|
||||
(TD)Vk->E2(2 * i + 1)); \
|
||||
} \
|
||||
}
|
||||
|
||||
VMADDWOD(vmaddwod_h_b, 16, H, B, DO_MUL)
|
||||
|
|
@ -593,40 +597,42 @@ VMADDWOD(vmaddwod_h_bu, 16, UH, UB, DO_MUL)
|
|||
VMADDWOD(vmaddwod_w_hu, 32, UW, UH, DO_MUL)
|
||||
VMADDWOD(vmaddwod_d_wu, 64, UD, UW, DO_MUL)
|
||||
|
||||
#define VMADDWEV_U_S(NAME, BIT, ES1, EU1, ES2, EU2, DO_OP) \
|
||||
void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t v) \
|
||||
{ \
|
||||
int i; \
|
||||
VReg *Vd = (VReg *)vd; \
|
||||
VReg *Vj = (VReg *)vj; \
|
||||
VReg *Vk = (VReg *)vk; \
|
||||
typedef __typeof(Vd->ES1(0)) TS1; \
|
||||
typedef __typeof(Vd->EU1(0)) TU1; \
|
||||
\
|
||||
for (i = 0; i < LSX_LEN/BIT; i++) { \
|
||||
Vd->ES1(i) += DO_OP((TU1)Vj->EU2(2 * i), \
|
||||
(TS1)Vk->ES2(2 * i)); \
|
||||
} \
|
||||
#define VMADDWEV_U_S(NAME, BIT, ES1, EU1, ES2, EU2, DO_OP) \
|
||||
void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
|
||||
{ \
|
||||
int i; \
|
||||
VReg *Vd = (VReg *)vd; \
|
||||
VReg *Vj = (VReg *)vj; \
|
||||
VReg *Vk = (VReg *)vk; \
|
||||
typedef __typeof(Vd->ES1(0)) TS1; \
|
||||
typedef __typeof(Vd->EU1(0)) TU1; \
|
||||
int oprsz = simd_oprsz(desc); \
|
||||
\
|
||||
for (i = 0; i < oprsz / (BIT / 8); i++) { \
|
||||
Vd->ES1(i) += DO_OP((TU1)Vj->EU2(2 * i), \
|
||||
(TS1)Vk->ES2(2 * i)); \
|
||||
} \
|
||||
}
|
||||
|
||||
VMADDWEV_U_S(vmaddwev_h_bu_b, 16, H, UH, B, UB, DO_MUL)
|
||||
VMADDWEV_U_S(vmaddwev_w_hu_h, 32, W, UW, H, UH, DO_MUL)
|
||||
VMADDWEV_U_S(vmaddwev_d_wu_w, 64, D, UD, W, UW, DO_MUL)
|
||||
|
||||
#define VMADDWOD_U_S(NAME, BIT, ES1, EU1, ES2, EU2, DO_OP) \
|
||||
void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t v) \
|
||||
{ \
|
||||
int i; \
|
||||
VReg *Vd = (VReg *)vd; \
|
||||
VReg *Vj = (VReg *)vj; \
|
||||
VReg *Vk = (VReg *)vk; \
|
||||
typedef __typeof(Vd->ES1(0)) TS1; \
|
||||
typedef __typeof(Vd->EU1(0)) TU1; \
|
||||
\
|
||||
for (i = 0; i < LSX_LEN/BIT; i++) { \
|
||||
Vd->ES1(i) += DO_OP((TU1)Vj->EU2(2 * i + 1), \
|
||||
(TS1)Vk->ES2(2 * i + 1)); \
|
||||
} \
|
||||
#define VMADDWOD_U_S(NAME, BIT, ES1, EU1, ES2, EU2, DO_OP) \
|
||||
void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
|
||||
{ \
|
||||
int i; \
|
||||
VReg *Vd = (VReg *)vd; \
|
||||
VReg *Vj = (VReg *)vj; \
|
||||
VReg *Vk = (VReg *)vk; \
|
||||
typedef __typeof(Vd->ES1(0)) TS1; \
|
||||
typedef __typeof(Vd->EU1(0)) TU1; \
|
||||
int oprsz = simd_oprsz(desc); \
|
||||
\
|
||||
for (i = 0; i < oprsz / (BIT / 8); i++) { \
|
||||
Vd->ES1(i) += DO_OP((TU1)Vj->EU2(2 * i + 1), \
|
||||
(TS1)Vk->ES2(2 * i + 1)); \
|
||||
} \
|
||||
}
|
||||
|
||||
VMADDWOD_U_S(vmaddwod_h_bu_b, 16, H, UH, B, UB, DO_MUL)
|
||||
|
|
|
|||
Loading…
Reference in New Issue