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target/loongarch: Rename MMU_IDX_* 

The expected form is MMU_FOO_IDX, not MMU_IDX_FOO.
Rename to match generic code.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2024-02-02 15:49:51 +10:00
parent a72a1b105d
commit 3f262d2568
5 changed files with 9 additions and 9 deletions
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2
target/loongarch/cpu.c
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@ -382,7 +382,7 @@ int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch)
if (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG)) { if (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG)) {
return FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV); return FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV);
} }
return MMU_IDX_DA; return MMU_DA_IDX;
} }
static void loongarch_la464_initfn(Object *obj) static void loongarch_la464_initfn(Object *obj)

8
target/loongarch/cpu.h
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@ -404,15 +404,15 @@ struct LoongArchCPUClass {
*/ */
#define MMU_PLV_KERNEL 0 #define MMU_PLV_KERNEL 0
#define MMU_PLV_USER 3 #define MMU_PLV_USER 3
#define MMU_IDX_KERNEL MMU_PLV_KERNEL #define MMU_KERNEL_IDX MMU_PLV_KERNEL
#define MMU_IDX_USER MMU_PLV_USER #define MMU_USER_IDX MMU_PLV_USER
#define MMU_IDX_DA 4 #define MMU_DA_IDX 4
int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch); int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch);
static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch) static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch)
{ {
#ifdef CONFIG_USER_ONLY #ifdef CONFIG_USER_ONLY
return MMU_IDX_USER; return MMU_USER_IDX;
#else #else
return loongarch_cpu_mmu_index(env_cpu(env), ifetch); return loongarch_cpu_mmu_index(env_cpu(env), ifetch);
#endif #endif

4
target/loongarch/cpu_helper.c
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@ -171,8 +171,8 @@ int get_physical_address(CPULoongArchState *env, hwaddr *physical,
int *prot, target_ulong address, int *prot, target_ulong address,
MMUAccessType access_type, int mmu_idx) MMUAccessType access_type, int mmu_idx)
{ {
int user_mode = mmu_idx == MMU_IDX_USER; int user_mode = mmu_idx == MMU_USER_IDX;
int kernel_mode = mmu_idx == MMU_IDX_KERNEL; int kernel_mode = mmu_idx == MMU_KERNEL_IDX;
uint32_t plv, base_c, base_v; uint32_t plv, base_c, base_v;
int64_t addr_high; int64_t addr_high;
uint8_t da = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, DA); uint8_t da = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, DA);

2
target/loongarch/tcg/insn_trans/trans_privileged.c.inc
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@ -323,7 +323,7 @@ TRANS(iocsrwr_d, IOCSR, gen_iocsrwr, gen_helper_iocsrwr_d)
static void check_mmu_idx(DisasContext *ctx) static void check_mmu_idx(DisasContext *ctx)
{ {
if (ctx->mem_idx != MMU_IDX_DA) { if (ctx->mem_idx != MMU_DA_IDX) {
tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next + 4); tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next + 4);
ctx->base.is_jmp = DISAS_EXIT; ctx->base.is_jmp = DISAS_EXIT;
} }

2
target/loongarch/tcg/translate.c
View File

@ -125,7 +125,7 @@ static void loongarch_tr_init_disas_context(DisasContextBase *dcbase,
if (ctx->base.tb->flags & HW_FLAGS_CRMD_PG) { if (ctx->base.tb->flags & HW_FLAGS_CRMD_PG) {
ctx->mem_idx = ctx->plv; ctx->mem_idx = ctx->plv;
} else { } else {
ctx->mem_idx = MMU_IDX_DA; ctx->mem_idx = MMU_DA_IDX;
} }
/* Bound the number of insns to execute to those left on the page. */ /* Bound the number of insns to execute to those left on the page. */