mirror of https://github.com/xemu-project/xemu.git
target/riscv: remove cpu->cfg.ext_v
Create a new "v" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVV. Instances of cpu->cfg.ext_v and similar are replaced with riscv_has_ext(env, RVV). Remove the old "v" property and 'ext_v' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230406180351.570807-17-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -883,7 +883,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
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}
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/* The V vector extension depends on the Zve64d extension */
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if (cpu->cfg.ext_v) {
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if (riscv_has_ext(env, RVV)) {
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cpu->cfg.ext_zve64d = true;
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}
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@ -1018,7 +1018,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
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cpu->cfg.ext_zksh = true;
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}
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if (cpu->cfg.ext_v) {
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if (riscv_has_ext(env, RVV)) {
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int vext_version = VEXT_VERSION_1_00_0;
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if (!is_power_of_2(cpu->cfg.vlen)) {
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error_setg(errp,
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@ -1175,7 +1175,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
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if (riscv_has_ext(env, RVH)) {
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ext |= RVH;
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}
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if (riscv_cpu_cfg(env)->ext_v) {
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if (riscv_has_ext(env, RVV)) {
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ext |= RVV;
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}
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if (riscv_has_ext(env, RVJ)) {
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@ -1513,6 +1513,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
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.misa_bit = RVH, .enabled = true},
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{.name = "x-j", .description = "Dynamic translated languages",
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.misa_bit = RVJ, .enabled = false},
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{.name = "v", .description = "Vector operations",
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.misa_bit = RVV, .enabled = false},
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};
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static void riscv_cpu_add_misa_properties(Object *cpu_obj)
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@ -1536,7 +1538,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
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static Property riscv_cpu_extensions[] = {
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/* Defaults for standard extensions */
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DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
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DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
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DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
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DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false),
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DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
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@ -1638,7 +1639,6 @@ static Property riscv_cpu_extensions[] = {
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static void register_cpu_props(Object *obj)
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{
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RISCVCPU *cpu = RISCV_CPU(obj);
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uint32_t misa_ext = cpu->env.misa_ext;
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Property *prop;
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DeviceState *dev = DEVICE(obj);
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@ -1648,8 +1648,6 @@ static void register_cpu_props(Object *obj)
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* later on.
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*/
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if (cpu->env.misa_ext != 0) {
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cpu->cfg.ext_v = misa_ext & RVV;
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/*
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* We don't want to set the default riscv_cpu_extensions
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* in this case.
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@ -423,7 +423,6 @@ typedef struct {
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struct RISCVCPUConfig {
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bool ext_g;
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bool ext_v;
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bool ext_zba;
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bool ext_zbb;
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bool ext_zbc;
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