ShuriZma
/
xemu
mirror of https://github.com/xemu-project/xemu.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Introduce 4KEm configuration with fixed MMU mapping. Delete bogus INSN_DSP 

flags.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3637 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
ths 2007-11-14 03:11:17 +00:00
parent 1b413d5563
commit 3e4587d5d1
1 changed files with 19 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
target-mips/translate_init.c
View File

@ -128,6 +128,23 @@ static mips_def_t mips_defs[] =
.CP0_Status_rw_bitmask = 0x1278FF17, .CP0_Status_rw_bitmask = 0x1278FF17,
.insn_flags = CPU_MIPS32R2 | ASE_MIPS16, .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
}, },
{
.name = "4KEm",
.CP0_PRid = 0x00019100,
/* Config1 implemented, MIPS32R2, fixed mapping MMU,
no virtual icache, uncached coherency. */
.CP0_Config0 = (1 << CP0C0_M) | (0x1 << CP0C0_AR) |
(0x3 << CP0C0_MT) | (0x2 << CP0C0_K0),
.CP0_Config1 = MIPS_CONFIG1 |
(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
.CP0_Config2 = MIPS_CONFIG2,
.CP0_Config3 = MIPS_CONFIG3,
.SYNCI_Step = 32,
.CCRes = 2,
.CP0_Status_rw_bitmask = 0x1258FF17,
.insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
},
{ {
.name = "24Kc", .name = "24Kc",
.CP0_PRid = 0x00019300, .CP0_PRid = 0x00019300,
@ -141,7 +158,7 @@ static mips_def_t mips_defs[] =
.CCRes = 2, .CCRes = 2,
/* No DSP implemented. */ /* No DSP implemented. */
.CP0_Status_rw_bitmask = 0x1278FF1F, .CP0_Status_rw_bitmask = 0x1278FF1F,
.insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP, .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
}, },
{ {
.name = "24Kf", .name = "24Kf",
@ -158,7 +175,7 @@ static mips_def_t mips_defs[] =
.CP0_Status_rw_bitmask = 0x3678FF1F, .CP0_Status_rw_bitmask = 0x3678FF1F,
.CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
(1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID), (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
.insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP, .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
}, },
{ {
.name = "34Kf", .name = "34Kf",