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hw/net: create common collection of MII definitions 

Create a common set of definitions of address and register values for
ethernet MII phys. A few of the current ethernet drivers have at least
a partial set of these definitions. Others just use hard coded raw
constant numbers.

This initial set is copied directly from the allwinner_emac code.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-id: 1435296436-12152-2-git-send-email-gerg@uclinux.org
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Greg Ungerer 2015-06-26 15:27:13 +10:00 committed by Stefan Hajnoczi
parent f793d97e45
commit 3e230569bf
2 changed files with 65 additions and 39 deletions
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40
include/hw/net/allwinner_emac.h
View File

@ -24,6 +24,7 @@
#include "net/net.h" #include "net/net.h"
#include "qemu/fifo8.h" #include "qemu/fifo8.h"
#include "hw/net/mii.h"
#define TYPE_AW_EMAC "allwinner-emac" #define TYPE_AW_EMAC "allwinner-emac"
#define AW_EMAC(obj) OBJECT_CHECK(AwEmacState, (obj), TYPE_AW_EMAC) #define AW_EMAC(obj) OBJECT_CHECK(AwEmacState, (obj), TYPE_AW_EMAC)
@ -118,45 +119,6 @@
#define EMAC_RX_IO_DATA_STATUS_OK (1 << 7) #define EMAC_RX_IO_DATA_STATUS_OK (1 << 7)
#define EMAC_UNDOCUMENTED_MAGIC 0x0143414d /* header for RX frames */ #define EMAC_UNDOCUMENTED_MAGIC 0x0143414d /* header for RX frames */
/* PHY registers */
#define MII_BMCR 0
#define MII_BMSR 1
#define MII_PHYID1 2
#define MII_PHYID2 3
#define MII_ANAR 4
#define MII_ANLPAR 5
#define MII_ANER 6
#define MII_NSR 16
#define MII_LBREMR 17
#define MII_REC 18
#define MII_SNRDR 19
#define MII_TEST 25
/* PHY registers fields */
#define MII_BMCR_RESET (1 << 15)
#define MII_BMCR_LOOPBACK (1 << 14)
#define MII_BMCR_SPEED (1 << 13)
#define MII_BMCR_AUTOEN (1 << 12)
#define MII_BMCR_FD (1 << 8)
#define MII_BMSR_100TX_FD (1 << 14)
#define MII_BMSR_100TX_HD (1 << 13)
#define MII_BMSR_10T_FD (1 << 12)
#define MII_BMSR_10T_HD (1 << 11)
#define MII_BMSR_MFPS (1 << 6)
#define MII_BMSR_AN_COMP (1 << 5)
#define MII_BMSR_AUTONEG (1 << 3)
#define MII_BMSR_LINK_ST (1 << 2)
#define MII_ANAR_TXFD (1 << 8)
#define MII_ANAR_TX (1 << 7)
#define MII_ANAR_10FD (1 << 6)
#define MII_ANAR_10 (1 << 5)
#define MII_ANAR_CSMACD (1 << 0)
#define RTL8201CP_PHYID1 0x0000
#define RTL8201CP_PHYID2 0x8201
/* INT CTL and INT STA registers fields */ /* INT CTL and INT STA registers fields */
#define EMAC_INT_TX_CHAN(x) (1 << (x)) #define EMAC_INT_TX_CHAN(x) (1 << (x))
#define EMAC_INT_RX (1 << 8) #define EMAC_INT_RX (1 << 8)

64
include/hw/net/mii.h Normal file
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@ -0,0 +1,64 @@
/*
* Common network MII address and register definitions.
*
* Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
*
* Allwinner EMAC register definitions from Linux kernel are:
* Copyright 2012 Stefan Roese <sr@denx.de>
* Copyright 2013 Maxime Ripard <maxime.ripard@free-electrons.com>
* Copyright 1997 Sten Wang
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef MII_H
#define MII_H
/* PHY registers */
#define MII_BMCR 0
#define MII_BMSR 1
#define MII_PHYID1 2
#define MII_PHYID2 3
#define MII_ANAR 4
#define MII_ANLPAR 5
#define MII_ANER 6
#define MII_NSR 16
#define MII_LBREMR 17
#define MII_REC 18
#define MII_SNRDR 19
#define MII_TEST 25
/* PHY registers fields */
#define MII_BMCR_RESET (1 << 15)
#define MII_BMCR_LOOPBACK (1 << 14)
#define MII_BMCR_SPEED (1 << 13)
#define MII_BMCR_AUTOEN (1 << 12)
#define MII_BMCR_FD (1 << 8)
#define MII_BMSR_100TX_FD (1 << 14)
#define MII_BMSR_100TX_HD (1 << 13)
#define MII_BMSR_10T_FD (1 << 12)
#define MII_BMSR_10T_HD (1 << 11)
#define MII_BMSR_MFPS (1 << 6)
#define MII_BMSR_AN_COMP (1 << 5)
#define MII_BMSR_AUTONEG (1 << 3)
#define MII_BMSR_LINK_ST (1 << 2)
#define MII_ANAR_TXFD (1 << 8)
#define MII_ANAR_TX (1 << 7)
#define MII_ANAR_10FD (1 << 6)
#define MII_ANAR_10 (1 << 5)
#define MII_ANAR_CSMACD (1 << 0)
/* List of vendor identifiers */
#define RTL8201CP_PHYID1 0x0000
#define RTL8201CP_PHYID2 0x8201
#endif /* MII_H */