mirror of https://github.com/xemu-project/xemu.git
cleanup nv2a
This commit is contained in:
espes
parent
3ee213e59a
commit
3d33d8101b
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@ -19,12 +19,27 @@
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include <assert.h>
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#include "qemu/osdep.h"
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#include "hw/display/vga_regs.h"
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#include "qemu/thread.h"
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#include "qemu/main-loop.h"
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#include "qapi/error.h"
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#include "qemu/error-report.h"
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#include "nv2a.h"
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#include <assert.h>
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#include "hw/hw.h"
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#include "hw/display/vga.h"
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#include "hw/display/vga_int.h"
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#include "hw/display/vga_regs.h"
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#include "hw/pci/pci.h"
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#include "cpu.h"
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#include "swizzle.h"
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#include "hw/xbox/nv2a/nv2a_int.h"
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#include "hw/xbox/nv2a/nv2a.h"
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#ifdef __WINNT__
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// HACK: mingw-w64 doesn't provide ffs, for now we just shove it here
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@ -45,7 +60,35 @@ int ffs(register int valu)
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}
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#endif
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void update_irq(NV2AState *d)
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#define DEFINE_PROTO(n) \
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uint64_t n##_read(void *opaque, hwaddr addr, unsigned int size); \
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void n##_write(void *opaque, hwaddr addr, uint64_t val, unsigned int size);
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DEFINE_PROTO(pmc)
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DEFINE_PROTO(pbus)
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DEFINE_PROTO(pfifo)
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DEFINE_PROTO(prma)
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DEFINE_PROTO(pvideo)
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DEFINE_PROTO(ptimer)
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DEFINE_PROTO(pcounter)
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DEFINE_PROTO(pvpe)
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DEFINE_PROTO(ptv)
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DEFINE_PROTO(prmfb)
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DEFINE_PROTO(prmvio)
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DEFINE_PROTO(pfb)
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DEFINE_PROTO(pstraps)
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DEFINE_PROTO(pgraph)
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DEFINE_PROTO(pcrtc)
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DEFINE_PROTO(prmcio)
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DEFINE_PROTO(pramdac)
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DEFINE_PROTO(prmdio)
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// DEFINE_PROTO(pramin)
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DEFINE_PROTO(user)
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#undef DEFINE_PROTO
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static void update_irq(NV2AState *d)
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{
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/* PFIFO */
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if (d->pfifo.pending_interrupts & d->pfifo.enabled_interrupts) {
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@ -76,7 +119,7 @@ void update_irq(NV2AState *d)
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}
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}
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DMAObject nv_dma_load(NV2AState *d, hwaddr dma_obj_address)
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static DMAObject nv_dma_load(NV2AState *d, hwaddr dma_obj_address)
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{
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assert(dma_obj_address < memory_region_size(&d->ramin));
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@ -93,7 +136,7 @@ DMAObject nv_dma_load(NV2AState *d, hwaddr dma_obj_address)
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};
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}
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void *nv_dma_map(NV2AState *d, hwaddr dma_obj_address, hwaddr *len)
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static void *nv_dma_map(NV2AState *d, hwaddr dma_obj_address, hwaddr *len)
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{
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DMAObject dma = nv_dma_load(d, dma_obj_address);
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@ -113,8 +156,8 @@ void *nv_dma_map(NV2AState *d, hwaddr dma_obj_address, hwaddr *len)
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#include "nv2a_pbus.c"
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#include "nv2a_pcrtc.c"
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#include "nv2a_pfb.c"
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#include "nv2a_pfifo.c"
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#include "nv2a_pgraph.c"
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#include "nv2a_pfifo.c"
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#include "nv2a_pmc.c"
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#include "nv2a_pramdac.c"
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#include "nv2a_prmcio.c"
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@ -157,39 +200,36 @@ const struct NV2ABlockInfo blocktable[] = {
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#undef ENTRY
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const int blocktable_len = ARRAY_SIZE(blocktable);
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static const char* nv2a_reg_names[] = {};
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// FIXME: Add nv2a_reg_names or remove this code
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// static const char* nv2a_reg_names[] = {};
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void reg_log_read(int block, hwaddr addr, uint64_t val)
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static void reg_log_read(int block, hwaddr addr, uint64_t val)
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{
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if (blocktable[block].name) {
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// hwaddr naddr = blocktable[block].offset + addr;
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// if (naddr < ARRAY_SIZE(nv2a_reg_names) && nv2a_reg_names[naddr]) {
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// NV2A_DPRINTF("%s: read [%s] -> 0x%" PRIx64 "\n",
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// blocktable[block].name, nv2a_reg_names[naddr], val);
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// } else {
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hwaddr naddr = blocktable[block].offset + addr;
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if (naddr < ARRAY_SIZE(nv2a_reg_names) && nv2a_reg_names[naddr]) {
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NV2A_DPRINTF("%s: read [%s] -> 0x%" PRIx64 "\n",
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blocktable[block].name, nv2a_reg_names[naddr], val);
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} else {
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NV2A_DPRINTF("%s: read [%" HWADDR_PRIx "] -> 0x%" PRIx64 "\n",
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blocktable[block].name, addr, val);
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// }
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}
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} else {
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NV2A_DPRINTF("(%d?): read [%" HWADDR_PRIx "] -> 0x%" PRIx64 "\n",
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block, addr, val);
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}
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}
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void reg_log_write(int block, hwaddr addr, uint64_t val)
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static void reg_log_write(int block, hwaddr addr, uint64_t val)
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{
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if (blocktable[block].name) {
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// hwaddr naddr = blocktable[block].offset + addr;
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// if (naddr < ARRAY_SIZE(nv2a_reg_names) && nv2a_reg_names[naddr]) {
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// NV2A_DPRINTF("%s: [%s] = 0x%" PRIx64 "\n",
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// blocktable[block].name, nv2a_reg_names[naddr], val);
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// } else {
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hwaddr naddr = blocktable[block].offset + addr;
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if (naddr < ARRAY_SIZE(nv2a_reg_names) && nv2a_reg_names[naddr]) {
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NV2A_DPRINTF("%s: [%s] = 0x%" PRIx64 "\n",
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blocktable[block].name, nv2a_reg_names[naddr], val);
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} else {
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NV2A_DPRINTF("%s: [%" HWADDR_PRIx "] = 0x%" PRIx64 "\n",
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blocktable[block].name, addr, val);
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// }
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}
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} else {
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NV2A_DPRINTF("(%d?): [%" HWADDR_PRIx "] = 0x%" PRIx64 "\n",
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block, addr, val);
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@ -2,8 +2,6 @@
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* QEMU Geforce NV2A implementation
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*
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* Copyright (c) 2012 espes
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* Copyright (c) 2015 Jannik Vogel
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* Copyright (c) 2018 Matt Borgerson
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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@ -22,369 +20,6 @@
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#ifndef HW_NV2A_H
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#define HW_NV2A_H
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#include "hw/hw.h"
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#include "hw/display/vga.h"
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#include "hw/display/vga_int.h"
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#include "hw/i386/pc.h"
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#include "hw/pci/pci.h"
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#include "qapi/qmp/qstring.h"
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#include "qemu/thread.h"
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#include "cpu.h"
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#include "g-lru-cache.h"
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#include "nv2a_debug.h"
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#include "nv2a_int.h"
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#include "nv2a_shaders.h"
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#include "swizzle.h"
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#include "gl/gloffscreen.h"
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#define USE_TEXTURE_CACHE
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#define GET_MASK(v, mask) (((v) & (mask)) >> (ffs(mask) - 1))
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#define SET_MASK(v, mask, val) \
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({ \
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const unsigned int __val = (val); \
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const unsigned int __mask = (mask); \
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(v) &= ~(__mask); \
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(v) |= ((__val) << (ffs(__mask) - 1)) & (__mask); \
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})
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#define CASE_4(v, step) \
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case (v): \
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case ((v) + (step)): \
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case ((v) + (step) * 2): \
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case ((v) + (step) * 3)
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#define NV2A_DEVICE(obj) OBJECT_CHECK(NV2AState, (obj), "nv2a")
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void reg_log_read(int block, hwaddr addr, uint64_t val);
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void reg_log_write(int block, hwaddr addr, uint64_t val);
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enum FIFOEngine {
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ENGINE_SOFTWARE = 0,
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ENGINE_GRAPHICS = 1,
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ENGINE_DVD = 2,
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};
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typedef struct DMAObject {
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unsigned int dma_class;
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unsigned int dma_target;
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hwaddr address;
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hwaddr limit;
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} DMAObject;
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typedef struct VertexAttribute {
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bool dma_select;
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hwaddr offset;
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/* inline arrays are packed in order?
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* Need to pass the offset to converted attributes */
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unsigned int inline_array_offset;
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float inline_value[4];
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unsigned int format;
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unsigned int size; /* size of the data type */
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unsigned int count; /* number of components */
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uint32_t stride;
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bool needs_conversion;
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uint8_t *converted_buffer;
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unsigned int converted_elements;
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unsigned int converted_size;
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unsigned int converted_count;
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float *inline_buffer;
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GLint gl_count;
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GLenum gl_type;
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GLboolean gl_normalize;
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GLuint gl_converted_buffer;
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GLuint gl_inline_buffer;
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} VertexAttribute;
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typedef struct Surface {
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bool draw_dirty;
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bool buffer_dirty;
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bool write_enabled_cache;
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unsigned int pitch;
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hwaddr offset;
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} Surface;
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typedef struct SurfaceShape {
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unsigned int z_format;
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unsigned int color_format;
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unsigned int zeta_format;
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unsigned int log_width, log_height;
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unsigned int clip_x, clip_y;
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unsigned int clip_width, clip_height;
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unsigned int anti_aliasing;
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} SurfaceShape;
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typedef struct TextureShape {
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bool cubemap;
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unsigned int dimensionality;
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unsigned int color_format;
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unsigned int levels;
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unsigned int width, height, depth;
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unsigned int min_mipmap_level, max_mipmap_level;
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unsigned int pitch;
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} TextureShape;
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typedef struct TextureKey {
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TextureShape state;
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uint64_t data_hash;
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uint8_t *texture_data;
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uint8_t *palette_data;
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} TextureKey;
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typedef struct TextureBinding {
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GLenum gl_target;
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GLuint gl_texture;
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unsigned int refcnt;
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} TextureBinding;
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typedef struct KelvinState {
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hwaddr object_instance;
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} KelvinState;
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typedef struct ContextSurfaces2DState {
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hwaddr object_instance;
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hwaddr dma_image_source;
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hwaddr dma_image_dest;
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unsigned int color_format;
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unsigned int source_pitch, dest_pitch;
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hwaddr source_offset, dest_offset;
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} ContextSurfaces2DState;
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typedef struct ImageBlitState {
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hwaddr object_instance;
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hwaddr context_surfaces;
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unsigned int operation;
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unsigned int in_x, in_y;
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unsigned int out_x, out_y;
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unsigned int width, height;
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} ImageBlitState;
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typedef struct PGRAPHState {
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QemuMutex lock;
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uint32_t pending_interrupts;
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uint32_t enabled_interrupts;
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QemuCond interrupt_cond;
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/* subchannels state we're not sure the location of... */
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ContextSurfaces2DState context_surfaces_2d;
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ImageBlitState image_blit;
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KelvinState kelvin;
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QemuCond fifo_access_cond;
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QemuCond flip_3d;
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hwaddr dma_color, dma_zeta;
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Surface surface_color, surface_zeta;
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unsigned int surface_type;
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SurfaceShape surface_shape;
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SurfaceShape last_surface_shape;
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hwaddr dma_a, dma_b;
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GLruCache *texture_cache;
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bool texture_dirty[NV2A_MAX_TEXTURES];
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TextureBinding *texture_binding[NV2A_MAX_TEXTURES];
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GHashTable *shader_cache;
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ShaderBinding *shader_binding;
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bool texture_matrix_enable[NV2A_MAX_TEXTURES];
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/* FIXME: Move to NV_PGRAPH_BUMPMAT... */
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float bump_env_matrix[NV2A_MAX_TEXTURES - 1][4]; /* 3 allowed stages with 2x2 matrix each */
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GloContext *gl_context;
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GLuint gl_framebuffer;
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GLuint gl_color_buffer, gl_zeta_buffer;
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hwaddr dma_state;
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hwaddr dma_notifies;
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hwaddr dma_semaphore;
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hwaddr dma_report;
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hwaddr report_offset;
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bool zpass_pixel_count_enable;
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unsigned int zpass_pixel_count_result;
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unsigned int gl_zpass_pixel_count_query_count;
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GLuint *gl_zpass_pixel_count_queries;
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hwaddr dma_vertex_a, dma_vertex_b;
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unsigned int primitive_mode;
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bool enable_vertex_program_write;
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uint32_t program_data[NV2A_MAX_TRANSFORM_PROGRAM_LENGTH][VSH_TOKEN_SIZE];
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uint32_t vsh_constants[NV2A_VERTEXSHADER_CONSTANTS][4];
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bool vsh_constants_dirty[NV2A_VERTEXSHADER_CONSTANTS];
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/* lighting constant arrays */
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uint32_t ltctxa[NV2A_LTCTXA_COUNT][4];
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bool ltctxa_dirty[NV2A_LTCTXA_COUNT];
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uint32_t ltctxb[NV2A_LTCTXB_COUNT][4];
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bool ltctxb_dirty[NV2A_LTCTXB_COUNT];
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uint32_t ltc1[NV2A_LTC1_COUNT][4];
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bool ltc1_dirty[NV2A_LTC1_COUNT];
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// should figure out where these are in lighting context
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float light_infinite_half_vector[NV2A_MAX_LIGHTS][3];
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float light_infinite_direction[NV2A_MAX_LIGHTS][3];
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float light_local_position[NV2A_MAX_LIGHTS][3];
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float light_local_attenuation[NV2A_MAX_LIGHTS][3];
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VertexAttribute vertex_attributes[NV2A_VERTEXSHADER_ATTRIBUTES];
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unsigned int inline_array_length;
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uint32_t inline_array[NV2A_MAX_BATCH_LENGTH];
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GLuint gl_inline_array_buffer;
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unsigned int inline_elements_length;
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uint32_t inline_elements[NV2A_MAX_BATCH_LENGTH];
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unsigned int inline_buffer_length;
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unsigned int draw_arrays_length;
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unsigned int draw_arrays_max_count;
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/* FIXME: Unknown size, possibly endless, 1000 will do for now */
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GLint gl_draw_arrays_start[1000];
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GLsizei gl_draw_arrays_count[1000];
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GLuint gl_element_buffer;
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GLuint gl_memory_buffer;
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GLuint gl_vertex_array;
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uint32_t regs[0x2000];
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} PGRAPHState;
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typedef struct NV2AState {
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PCIDevice dev;
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qemu_irq irq;
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bool exiting;
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VGACommonState vga;
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GraphicHwOps hw_ops;
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QEMUTimer *vblank_timer;
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MemoryRegion *vram;
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MemoryRegion vram_pci;
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uint8_t *vram_ptr;
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MemoryRegion ramin;
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uint8_t *ramin_ptr;
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MemoryRegion mmio;
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MemoryRegion block_mmio[NV_NUM_BLOCKS];
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struct {
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uint32_t pending_interrupts;
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uint32_t enabled_interrupts;
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} pmc;
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struct {
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uint32_t pending_interrupts;
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uint32_t enabled_interrupts;
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uint32_t regs[0x2000];
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QemuMutex lock;
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QemuThread puller_thread;
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QemuCond puller_cond;
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QemuThread pusher_thread;
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QemuCond pusher_cond;
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} pfifo;
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struct {
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uint32_t regs[0x1000];
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} pvideo;
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struct {
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uint32_t pending_interrupts;
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uint32_t enabled_interrupts;
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uint32_t numerator;
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uint32_t denominator;
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uint32_t alarm_time;
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} ptimer;
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struct {
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uint32_t regs[0x1000];
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} pfb;
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struct PGRAPHState pgraph;
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struct {
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uint32_t pending_interrupts;
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uint32_t enabled_interrupts;
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hwaddr start;
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} pcrtc;
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struct {
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uint32_t core_clock_coeff;
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uint64_t core_clock_freq;
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uint32_t memory_clock_coeff;
|
||||
uint32_t video_clock_coeff;
|
||||
} pramdac;
|
||||
|
||||
} NV2AState;
|
||||
|
||||
typedef struct NV2ABlockInfo {
|
||||
const char *name;
|
||||
hwaddr offset;
|
||||
uint64_t size;
|
||||
MemoryRegionOps ops;
|
||||
} NV2ABlockInfo;
|
||||
|
||||
extern const struct NV2ABlockInfo blocktable[];
|
||||
extern const int blocktable_len;
|
||||
|
||||
DMAObject nv_dma_load(NV2AState *d, hwaddr dma_obj_address);
|
||||
void *nv_dma_map(NV2AState *d, hwaddr dma_obj_address, hwaddr *len);
|
||||
void nv2a_init(PCIBus *bus, int devfn, MemoryRegion *ram);
|
||||
void pgraph_init(NV2AState *d);
|
||||
void *pfifo_puller_thread(void *opaque);
|
||||
void pgraph_destroy(PGRAPHState *pg);
|
||||
void update_irq(NV2AState *d);
|
||||
void pgraph_context_switch(NV2AState *d, unsigned int channel_id);
|
||||
void pgraph_wait_fifo_access(NV2AState *d);
|
||||
void pgraph_method(NV2AState *d,
|
||||
unsigned int subchannel,
|
||||
unsigned int method,
|
||||
uint32_t parameter);
|
||||
|
||||
#define DEFINE_PROTO(n) \
|
||||
uint64_t n##_read(void *opaque, hwaddr addr, unsigned int size); \
|
||||
void n##_write(void *opaque, hwaddr addr, uint64_t val, unsigned int size);
|
||||
|
||||
DEFINE_PROTO(pmc)
|
||||
DEFINE_PROTO(pbus)
|
||||
DEFINE_PROTO(pfifo)
|
||||
DEFINE_PROTO(prma)
|
||||
DEFINE_PROTO(pvideo)
|
||||
DEFINE_PROTO(ptimer)
|
||||
DEFINE_PROTO(pcounter)
|
||||
DEFINE_PROTO(pvpe)
|
||||
DEFINE_PROTO(ptv)
|
||||
DEFINE_PROTO(prmfb)
|
||||
DEFINE_PROTO(prmvio)
|
||||
DEFINE_PROTO(pfb)
|
||||
DEFINE_PROTO(pstraps)
|
||||
DEFINE_PROTO(pgraph)
|
||||
DEFINE_PROTO(pcrtc)
|
||||
DEFINE_PROTO(prmcio)
|
||||
DEFINE_PROTO(pramdac)
|
||||
DEFINE_PROTO(prmdio)
|
||||
// DEFINE_PROTO(pramin)
|
||||
DEFINE_PROTO(user)
|
||||
|
||||
#undef DEFINE_PROTO
|
||||
|
||||
#endif
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -204,7 +204,7 @@ static void pfifo_run_puller(NV2AState *d)
|
|||
}
|
||||
}
|
||||
|
||||
void* pfifo_puller_thread(void *arg)
|
||||
static void* pfifo_puller_thread(void *arg)
|
||||
{
|
||||
NV2AState *d = (NV2AState *)arg;
|
||||
|
||||
|
|
|
|||
|
|
@ -394,7 +394,7 @@ void pgraph_write(void *opaque, hwaddr addr, uint64_t val, unsigned int size)
|
|||
qemu_mutex_unlock(&d->pgraph.lock);
|
||||
}
|
||||
|
||||
void pgraph_method(NV2AState *d,
|
||||
static void pgraph_method(NV2AState *d,
|
||||
unsigned int subchannel,
|
||||
unsigned int method,
|
||||
uint32_t parameter)
|
||||
|
|
@ -2509,7 +2509,7 @@ void pgraph_method(NV2AState *d,
|
|||
}
|
||||
}
|
||||
|
||||
void pgraph_context_switch(NV2AState *d, unsigned int channel_id)
|
||||
static void pgraph_context_switch(NV2AState *d, unsigned int channel_id)
|
||||
{
|
||||
bool channel_valid =
|
||||
d->pgraph.regs[NV_PGRAPH_CTX_CONTROL] & NV_PGRAPH_CTX_CONTROL_CHID;
|
||||
|
|
@ -2541,7 +2541,7 @@ void pgraph_context_switch(NV2AState *d, unsigned int channel_id)
|
|||
}
|
||||
}
|
||||
|
||||
void pgraph_wait_fifo_access(NV2AState *d) {
|
||||
static void pgraph_wait_fifo_access(NV2AState *d) {
|
||||
while (!(d->pgraph.regs[NV_PGRAPH_FIFO] & NV_PGRAPH_FIFO_ACCESS)) {
|
||||
qemu_cond_wait(&d->pgraph.fifo_access_cond, &d->pgraph.lock);
|
||||
}
|
||||
|
|
@ -2630,7 +2630,7 @@ static void pgraph_finish_inline_buffer_vertex(PGRAPHState *pg)
|
|||
pg->inline_buffer_length++;
|
||||
}
|
||||
|
||||
void pgraph_init(NV2AState *d)
|
||||
static void pgraph_init(NV2AState *d)
|
||||
{
|
||||
int i;
|
||||
|
||||
|
|
@ -2717,7 +2717,7 @@ void pgraph_init(NV2AState *d)
|
|||
glo_set_current(NULL);
|
||||
}
|
||||
|
||||
void pgraph_destroy(PGRAPHState *pg)
|
||||
static void pgraph_destroy(PGRAPHState *pg)
|
||||
{
|
||||
qemu_mutex_destroy(&pg->lock);
|
||||
qemu_cond_destroy(&pg->interrupt_cond);
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -26,8 +26,7 @@
|
|||
|
||||
#include "nv2a_vsh.h"
|
||||
#include "nv2a_psh.h"
|
||||
#include "nv2a_int.h"
|
||||
|
||||
#include "nv2a_regs.h"
|
||||
|
||||
enum ShaderPrimitiveMode {
|
||||
PRIM_TYPE_NONE,
|
||||
|
|
|
|||
|
|
@ -49,12 +49,10 @@
|
|||
|
||||
#include "hw/xbox/xbox_pci.h"
|
||||
#include "hw/xbox/smbus.h"
|
||||
|
||||
#include "hw/xbox/nv2a/nv2a.h"
|
||||
|
||||
#include "hw/xbox/xbox.h"
|
||||
|
||||
/* FIXME: Move to header file */
|
||||
void nv2a_init(PCIBus *bus, int devfn, MemoryRegion *ram);
|
||||
|
||||
#define MAX_IDE_BUS 2
|
||||
|
||||
// XBOX_TODO: Should be passed in through configuration
|
||||
|
|
|
|||
Loading…
Reference in New Issue