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Compile pflash_cfi01 only once 

Push TARGET_WORDS_BIGENDIAN dependency to board level.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Blue Swirl 2010-03-29 19:23:56 +00:00
parent 5f9fc5ad7e
commit 3d08ff698b
16 changed files with 194 additions and 91 deletions
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1
Makefile.objs
View File

@ -135,6 +135,7 @@ hw-obj-y += watchdog.o
hw-obj-$(CONFIG_ISA_MMIO) += isa_mmio.o
hw-obj-$(CONFIG_ECC) += ecc.o
hw-obj-$(CONFIG_NAND) += nand.o
hw-obj-$(CONFIG_PFLASH_CFI01) += pflash_cfi01.o
hw-obj-$(CONFIG_PFLASH_CFI02) += pflash_cfi02.o
hw-obj-$(CONFIG_M48T59) += m48t59.o

5
Makefile.target
View File

@ -215,7 +215,6 @@ obj-mips-y += dma.o vga.o i8259.o
obj-mips-y += g364fb.o jazz_led.o
obj-mips-y += gt64xxx.o pckbd.o mc146818rtc.o
obj-mips-y += piix4.o cirrus_vga.o
obj-mips-y += pflash_cfi01.o
obj-microblaze-y = petalogix_s3adsp1800_mmu.o
@ -225,8 +224,6 @@ obj-microblaze-y += xilinx_timer.o
obj-microblaze-y += xilinx_uartlite.o
obj-microblaze-y += xilinx_ethlite.o
obj-microblaze-y += pflash_cfi01.o
obj-microblaze-$(CONFIG_FDT) += device_tree.o
# Boards
@ -259,7 +256,7 @@ obj-arm-y += pl061.o
obj-arm-y += arm-semi.o
obj-arm-y += pxa2xx.o pxa2xx_pic.o pxa2xx_gpio.o pxa2xx_timer.o pxa2xx_dma.o
obj-arm-y += pxa2xx_lcd.o pxa2xx_mmci.o pxa2xx_pcmcia.o pxa2xx_keypad.o
obj-arm-y += pflash_cfi01.o gumstix.o
obj-arm-y += gumstix.o
obj-arm-y += zaurus.o ide/microdrive.o spitz.o tosa.o tc6393xb.o
obj-arm-y += omap1.o omap_lcdc.o omap_dma.o omap_clk.o omap_mmc.o omap_i2c.o
obj-arm-y += omap2.o omap_dss.o soc_dma.o

1
default-configs/arm-softmmu.mak
View File

@ -26,4 +26,5 @@ CONFIG_LAN9118=y
CONFIG_SMC91C111=y
CONFIG_DS1338=y
CONFIG_VIRTIO_PCI=y
CONFIG_PFLASH_CFI01=y
CONFIG_PFLASH_CFI02=y

1
default-configs/microblaze-softmmu.mak
View File

@ -2,3 +2,4 @@
CONFIG_PTIMER=y
CONFIG_VIRTIO_PCI=y
CONFIG_PFLASH_CFI01=y

1
default-configs/mips-softmmu.mak
View File

@ -25,3 +25,4 @@ CONFIG_RC4030=y
CONFIG_DP8393X=y
CONFIG_DS1225Y=y
CONFIG_MIPSNET=y
CONFIG_PFLASH_CFI01=y

1
default-configs/mips64-softmmu.mak
View File

@ -25,3 +25,4 @@ CONFIG_RC4030=y
CONFIG_DP8393X=y
CONFIG_DS1225Y=y
CONFIG_MIPSNET=y
CONFIG_PFLASH_CFI01=y

1
default-configs/mips64el-softmmu.mak
View File

@ -25,3 +25,4 @@ CONFIG_RC4030=y
CONFIG_DP8393X=y
CONFIG_DS1225Y=y
CONFIG_MIPSNET=y
CONFIG_PFLASH_CFI01=y

1
default-configs/mipsel-softmmu.mak
View File

@ -25,3 +25,4 @@ CONFIG_RC4030=y
CONFIG_DP8393X=y
CONFIG_DS1225Y=y
CONFIG_MIPSNET=y
CONFIG_PFLASH_CFI01=y

2
hw/flash.h
View File

@ -6,7 +6,7 @@ pflash_t *pflash_cfi01_register(target_phys_addr_t base, ram_addr_t off,
BlockDriverState *bs,
uint32_t sector_len, int nb_blocs, int width,
uint16_t id0, uint16_t id1,
uint16_t id2, uint16_t id3);
uint16_t id2, uint16_t id3, int be);
/* pflash_cfi02.c */
pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off,

20
hw/gumstix.c
View File

@ -48,6 +48,7 @@ static void connex_init(ram_addr_t ram_size,
{
PXA2xxState *cpu;
DriveInfo *dinfo;
int be;
uint32_t connex_rom = 0x01000000;
uint32_t connex_ram = 0x04000000;
@ -61,9 +62,14 @@ static void connex_init(ram_addr_t ram_size,
exit(1);
}
#ifdef TARGET_WORDS_BIGENDIAN
be = 1;
#else
be = 0;
#endif
if (!pflash_cfi01_register(0x00000000, qemu_ram_alloc(connex_rom),
dinfo->bdrv, sector_len, connex_rom / sector_len,
2, 0, 0, 0, 0)) {
dinfo->bdrv, sector_len, connex_rom / sector_len,
2, 0, 0, 0, 0, be)) {
fprintf(stderr, "qemu: Error registering flash memory.\n");
exit(1);
}
@ -82,6 +88,7 @@ static void verdex_init(ram_addr_t ram_size,
{
PXA2xxState *cpu;
DriveInfo *dinfo;
int be;
uint32_t verdex_rom = 0x02000000;
uint32_t verdex_ram = 0x10000000;
@ -95,9 +102,14 @@ static void verdex_init(ram_addr_t ram_size,
exit(1);
}
#ifdef TARGET_WORDS_BIGENDIAN
be = 1;
#else
be = 0;
#endif
if (!pflash_cfi01_register(0x00000000, qemu_ram_alloc(verdex_rom),
dinfo->bdrv, sector_len, verdex_rom / sector_len,
2, 0, 0, 0, 0)) {
dinfo->bdrv, sector_len, verdex_rom / sector_len,
2, 0, 0, 0, 0, be)) {
fprintf(stderr, "qemu: Error registering flash memory.\n");
exit(1);
}

13
hw/mainstone.c
View File

@ -79,6 +79,7 @@ static void mainstone_common_init(ram_addr_t ram_size,
qemu_irq *mst_irq;
DriveInfo *dinfo;
int i;
int be;
if (!cpu_model)
cpu_model = "pxa270-c5";
@ -91,6 +92,11 @@ static void mainstone_common_init(ram_addr_t ram_size,
/* Setup initial (reset) machine state */
cpu->env->regs[15] = mainstone_binfo.loader_start;
#ifdef TARGET_WORDS_BIGENDIAN
be = 1;
#else
be = 0;
#endif
/* There are two 32MiB flash devices on the board */
for (i = 0; i < 2; i ++) {
dinfo = drive_get(IF_PFLASH, 0, i);
@ -101,9 +107,10 @@ static void mainstone_common_init(ram_addr_t ram_size,
}
if (!pflash_cfi01_register(mainstone_flash_base[i],
qemu_ram_alloc(MAINSTONE_FLASH),
dinfo->bdrv, sector_len,
MAINSTONE_FLASH / sector_len, 4, 0, 0, 0, 0)) {
qemu_ram_alloc(MAINSTONE_FLASH),
dinfo->bdrv, sector_len,
MAINSTONE_FLASH / sector_len, 4, 0, 0, 0, 0,
be)) {
fprintf(stderr, "qemu: Error registering flash memory.\n");
exit(1);
}

8
hw/mips_malta.c
View File

@ -789,6 +789,7 @@ void mips_malta_init (ram_addr_t ram_size,
DriveInfo *fd[MAX_FD];
int fl_idx = 0;
int fl_sectors = 0;
int be;
/* Make sure the first 3 serial ports are associated with a device. */
for(i = 0; i < 3; i++) {
@ -833,6 +834,11 @@ void mips_malta_init (ram_addr_t ram_size,
cpu_register_physical_memory(0x1fc00000LL,
BIOS_SIZE, bios_offset | IO_MEM_ROM);
#ifdef TARGET_WORDS_BIGENDIAN
be = 1;
#else
be = 0;
#endif
/* FPGA */
malta_fpga = malta_fpga_init(0x1f000000LL, env->irq[2], serial_hds[2]);
@ -859,7 +865,7 @@ void mips_malta_init (ram_addr_t ram_size,
#endif
pflash_cfi01_register(0x1e000000LL, bios_offset,
dinfo->bdrv, 65536, fl_sectors,
4, 0x0000, 0x0000, 0x0000, 0x0000);
4, 0x0000, 0x0000, 0x0000, 0x0000, be);
fl_idx++;
} else {
/* Load a BIOS image. */

11
hw/mips_r4k.c
View File

@ -170,6 +170,7 @@ void mips_r4k_init (ram_addr_t ram_size,
qemu_irq *i8259;
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
DriveInfo *dinfo;
int be;
/* init CPUs */
if (cpu_model == NULL) {
@ -218,6 +219,11 @@ void mips_r4k_init (ram_addr_t ram_size,
} else {
bios_size = -1;
}
#ifdef TARGET_WORDS_BIGENDIAN
be = 1;
#else
be = 0;
#endif
if ((bios_size > 0) && (bios_size <= BIOS_SIZE)) {
bios_offset = qemu_ram_alloc(BIOS_SIZE);
cpu_register_physical_memory(0x1fc00000, BIOS_SIZE,
@ -228,8 +234,9 @@ void mips_r4k_init (ram_addr_t ram_size,
uint32_t mips_rom = 0x00400000;
bios_offset = qemu_ram_alloc(mips_rom);
if (!pflash_cfi01_register(0x1fc00000, bios_offset,
dinfo->bdrv, sector_len, mips_rom / sector_len,
4, 0, 0, 0, 0)) {
dinfo->bdrv, sector_len,
mips_rom / sector_len,
4, 0, 0, 0, 0, be)) {
fprintf(stderr, "qemu: Error registering flash memory.\n");
}
}

16
hw/omap_sx1.c
View File

@ -130,6 +130,7 @@ static void sx1_init(ram_addr_t ram_size,
DriveInfo *dinfo;
int fl_idx;
uint32_t flash_size = flash0_size;
int be;
if (version == 2) {
flash_size = flash2_size;
@ -150,11 +151,17 @@ static void sx1_init(ram_addr_t ram_size,
cpu_register_physical_memory(OMAP_CS3_BASE, OMAP_CS3_SIZE, io);
fl_idx = 0;
#ifdef TARGET_WORDS_BIGENDIAN
be = 1;
#else
be = 0;
#endif
if ((dinfo = drive_get(IF_PFLASH, 0, fl_idx)) != NULL) {
if (!pflash_cfi01_register(OMAP_CS0_BASE, qemu_ram_alloc(flash_size),
dinfo->bdrv, sector_size, flash_size / sector_size,
4, 0, 0, 0, 0)) {
dinfo->bdrv, sector_size,
flash_size / sector_size,
4, 0, 0, 0, 0, be)) {
fprintf(stderr, "qemu: Error registering flash memory %d.\n",
fl_idx);
}
@ -171,8 +178,9 @@ static void sx1_init(ram_addr_t ram_size,
OMAP_CS1_SIZE - flash1_size, io);
if (!pflash_cfi01_register(OMAP_CS1_BASE, qemu_ram_alloc(flash1_size),
dinfo->bdrv, sector_size, flash1_size / sector_size,
4, 0, 0, 0, 0)) {
dinfo->bdrv, sector_size,
flash1_size / sector_size,
4, 0, 0, 0, 0, be)) {
fprintf(stderr, "qemu: Error registering flash memory %d.\n",
fl_idx);
}

2
hw/petalogix_s3adsp1800_mmu.c
View File

@ -149,7 +149,7 @@ petalogix_s3adsp1800_init(ram_addr_t ram_size,
pflash_cfi01_register(0xa0000000, phys_flash,
dinfo ? dinfo->bdrv : NULL, (64 * 1024),
FLASH_SIZE >> 16,
1, 0x89, 0x18, 0x0000, 0x0);
1, 0x89, 0x18, 0x0000, 0x0, 1);
cpu_irq = microblaze_pic_init_cpu(env);
dev = xilinx_intc_create(0x81800000, cpu_irq[0], 2);

201
hw/pflash_cfi01.c
View File

@ -97,7 +97,7 @@ static void pflash_timer (void *opaque)
}
static uint32_t pflash_read (pflash_t *pfl, target_phys_addr_t offset,
int width)
int width, int be)
{
target_phys_addr_t boff;
uint32_t ret;
@ -126,29 +126,29 @@ static uint32_t pflash_read (pflash_t *pfl, target_phys_addr_t offset,
__func__, offset, ret);
break;
case 2:
#if defined(TARGET_WORDS_BIGENDIAN)
ret = p[offset] << 8;
ret |= p[offset + 1];
#else
ret = p[offset];
ret |= p[offset + 1] << 8;
#endif
if (be) {
ret = p[offset] << 8;
ret |= p[offset + 1];
} else {
ret = p[offset];
ret |= p[offset + 1] << 8;
}
DPRINTF("%s: data offset " TARGET_FMT_plx " %04x\n",
__func__, offset, ret);
break;
case 4:
#if defined(TARGET_WORDS_BIGENDIAN)
ret = p[offset] << 24;
ret |= p[offset + 1] << 16;
ret |= p[offset + 2] << 8;
ret |= p[offset + 3];
#else
ret = p[offset];
ret |= p[offset + 1] << 8;
ret |= p[offset + 1] << 8;
ret |= p[offset + 2] << 16;
ret |= p[offset + 3] << 24;
#endif
if (be) {
ret = p[offset] << 24;
ret |= p[offset + 1] << 16;
ret |= p[offset + 2] << 8;
ret |= p[offset + 3];
} else {
ret = p[offset];
ret |= p[offset + 1] << 8;
ret |= p[offset + 1] << 8;
ret |= p[offset + 2] << 16;
ret |= p[offset + 3] << 24;
}
DPRINTF("%s: data offset " TARGET_FMT_plx " %08x\n",
__func__, offset, ret);
break;
@ -197,7 +197,7 @@ static void pflash_update(pflash_t *pfl, int offset,
}
static inline void pflash_data_write(pflash_t *pfl, target_phys_addr_t offset,
uint32_t value, int width)
uint32_t value, int width, int be)
{
uint8_t *p = pfl->storage;
@ -209,33 +209,33 @@ static inline void pflash_data_write(pflash_t *pfl, target_phys_addr_t offset,
p[offset] = value;
break;
case 2:
#if defined(TARGET_WORDS_BIGENDIAN)
p[offset] = value >> 8;
p[offset + 1] = value;
#else
p[offset] = value;
p[offset + 1] = value >> 8;
#endif
if (be) {
p[offset] = value >> 8;
p[offset + 1] = value;
} else {
p[offset] = value;
p[offset + 1] = value >> 8;
}
break;
case 4:
#if defined(TARGET_WORDS_BIGENDIAN)
p[offset] = value >> 24;
p[offset + 1] = value >> 16;
p[offset + 2] = value >> 8;
p[offset + 3] = value;
#else
p[offset] = value;
p[offset + 1] = value >> 8;
p[offset + 2] = value >> 16;
p[offset + 3] = value >> 24;
#endif
if (be) {
p[offset] = value >> 24;
p[offset + 1] = value >> 16;
p[offset + 2] = value >> 8;
p[offset + 3] = value;
} else {
p[offset] = value;
p[offset + 1] = value >> 8;
p[offset + 2] = value >> 16;
p[offset + 3] = value >> 24;
}
break;
}
}
static void pflash_write(pflash_t *pfl, target_phys_addr_t offset,
uint32_t value, int width)
uint32_t value, int width, int be)
{
uint8_t *p;
uint8_t cmd;
@ -304,7 +304,7 @@ static void pflash_write(pflash_t *pfl, target_phys_addr_t offset,
case 0x10: /* Single Byte Program */
case 0x40: /* Single Byte Program */
DPRINTF("%s: Single Byte Program\n", __func__);
pflash_data_write(pfl, offset, value, width);
pflash_data_write(pfl, offset, value, width, be);
pflash_update(pfl, offset, width);
pfl->status |= 0x80; /* Ready! */
pfl->wcycle = 0;
@ -353,7 +353,7 @@ static void pflash_write(pflash_t *pfl, target_phys_addr_t offset,
case 2:
switch (pfl->cmd) {
case 0xe8: /* Block write */
pflash_data_write(pfl, offset, value, width);
pflash_data_write(pfl, offset, value, width, be);
pfl->status |= 0x80;
@ -412,57 +412,110 @@ static void pflash_write(pflash_t *pfl, target_phys_addr_t offset,
}
static uint32_t pflash_readb (void *opaque, target_phys_addr_t addr)
static uint32_t pflash_readb_be(void *opaque, target_phys_addr_t addr)
{
return pflash_read(opaque, addr, 1);
return pflash_read(opaque, addr, 1, 1);
}
static uint32_t pflash_readw (void *opaque, target_phys_addr_t addr)
static uint32_t pflash_readb_le(void *opaque, target_phys_addr_t addr)
{
return pflash_read(opaque, addr, 1, 0);
}
static uint32_t pflash_readw_be(void *opaque, target_phys_addr_t addr)
{
pflash_t *pfl = opaque;
return pflash_read(pfl, addr, 2);
return pflash_read(pfl, addr, 2, 1);
}
static uint32_t pflash_readl (void *opaque, target_phys_addr_t addr)
static uint32_t pflash_readw_le(void *opaque, target_phys_addr_t addr)
{
pflash_t *pfl = opaque;
return pflash_read(pfl, addr, 4);
return pflash_read(pfl, addr, 2, 0);
}
static void pflash_writeb (void *opaque, target_phys_addr_t addr,
uint32_t value)
{
pflash_write(opaque, addr, value, 1);
}
static void pflash_writew (void *opaque, target_phys_addr_t addr,
uint32_t value)
static uint32_t pflash_readl_be(void *opaque, target_phys_addr_t addr)
{
pflash_t *pfl = opaque;
pflash_write(pfl, addr, value, 2);
return pflash_read(pfl, addr, 4, 1);
}
static void pflash_writel (void *opaque, target_phys_addr_t addr,
uint32_t value)
static uint32_t pflash_readl_le(void *opaque, target_phys_addr_t addr)
{
pflash_t *pfl = opaque;
pflash_write(pfl, addr, value, 4);
return pflash_read(pfl, addr, 4, 0);
}
static CPUWriteMemoryFunc * const pflash_write_ops[] = {
&pflash_writeb,
&pflash_writew,
&pflash_writel,
static void pflash_writeb_be(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
pflash_write(opaque, addr, value, 1, 1);
}
static void pflash_writeb_le(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
pflash_write(opaque, addr, value, 1, 0);
}
static void pflash_writew_be(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
pflash_t *pfl = opaque;
pflash_write(pfl, addr, value, 2, 1);
}
static void pflash_writew_le(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
pflash_t *pfl = opaque;
pflash_write(pfl, addr, value, 2, 0);
}
static void pflash_writel_be(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
pflash_t *pfl = opaque;
pflash_write(pfl, addr, value, 4, 1);
}
static void pflash_writel_le(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
pflash_t *pfl = opaque;
pflash_write(pfl, addr, value, 4, 0);
}
static CPUWriteMemoryFunc * const pflash_write_ops_be[] = {
&pflash_writeb_be,
&pflash_writew_be,
&pflash_writel_be,
};
static CPUReadMemoryFunc * const pflash_read_ops[] = {
&pflash_readb,
&pflash_readw,
&pflash_readl,
static CPUReadMemoryFunc * const pflash_read_ops_be[] = {
&pflash_readb_be,
&pflash_readw_be,
&pflash_readl_be,
};
static CPUWriteMemoryFunc * const pflash_write_ops_le[] = {
&pflash_writeb_le,
&pflash_writew_le,
&pflash_writel_le,
};
static CPUReadMemoryFunc * const pflash_read_ops_le[] = {
&pflash_readb_le,
&pflash_readw_le,
&pflash_readl_le,
};
/* Count trailing zeroes of a 32 bits quantity */
@ -503,7 +556,8 @@ pflash_t *pflash_cfi01_register(target_phys_addr_t base, ram_addr_t off,
BlockDriverState *bs, uint32_t sector_len,
int nb_blocs, int width,
uint16_t id0, uint16_t id1,
uint16_t id2, uint16_t id3)
uint16_t id2, uint16_t id3,
int be)
{
pflash_t *pfl;
target_phys_addr_t total_len;
@ -522,8 +576,13 @@ pflash_t *pflash_cfi01_register(target_phys_addr_t base, ram_addr_t off,
/* FIXME: Allocate ram ourselves. */
pfl->storage = qemu_get_ram_ptr(off);
pfl->fl_mem = cpu_register_io_memory(
pflash_read_ops, pflash_write_ops, pfl);
if (be) {
pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_be,
pflash_write_ops_be, pfl);
} else {
pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_le,
pflash_write_ops_le, pfl);
}
pfl->off = off;
cpu_register_physical_memory(base, total_len,
off | pfl->fl_mem | IO_MEM_ROMD);