mirror of https://github.com/xemu-project/xemu.git
target/arm: Correct minor errors in Cortex-A710 definition
Correct a couple of minor errors in the Cortex-A710 definition:
* ID_AA64DFR0_EL1.DebugVer is 9 (indicating Armv8.4 debug architecture)
* ID_AA64ISAR1_EL1.APA is 5 (indicating more PAuth support)
* there is an IMPDEF CPUCFR_EL1, like that on the Neoverse-N1
Fixes: e3d45c0a89
("target/arm: Implement cortex-a710")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20230915185453.1871167-2-peter.maydell@linaro.org
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@ -840,6 +840,13 @@ static const ARMCPRegInfo cortex_a710_cp_reginfo[] = {
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{ .name = "CPUPFR_EL3", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 6,
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.access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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/*
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* Report CPUCFR_EL1.SCU as 1, as we do not implement the DSU
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* (and in particular its system registers).
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*/
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{ .name = "CPUCFR_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 0,
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.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 4 },
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/*
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* Stub RAMINDEX, as we don't actually implement caches, BTB,
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@ -909,12 +916,12 @@ static void aarch64_a710_initfn(Object *obj)
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cpu->isar.id_aa64pfr0 = 0x1201111120111112ull; /* GIC filled in later */
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cpu->isar.id_aa64pfr1 = 0x0000000000000221ull;
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cpu->isar.id_aa64zfr0 = 0x0000110100110021ull; /* with Crypto */
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cpu->isar.id_aa64dfr0 = 0x000011f010305611ull;
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cpu->isar.id_aa64dfr0 = 0x000011f010305619ull;
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cpu->isar.id_aa64dfr1 = 0;
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cpu->id_aa64afr0 = 0;
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cpu->id_aa64afr1 = 0;
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cpu->isar.id_aa64isar0 = 0x0221111110212120ull; /* with Crypto */
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cpu->isar.id_aa64isar1 = 0x0010111101211032ull;
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cpu->isar.id_aa64isar1 = 0x0010111101211052ull;
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cpu->isar.id_aa64mmfr0 = 0x0000022200101122ull;
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cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
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cpu->isar.id_aa64mmfr2 = 0x1221011110101011ull;
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