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ppc/pnv: Add an LPAR per core machine option 

Recent POWER CPUs can operate in "LPAR per core" or "LPAR per thread"
modes. In per-core mode, some SPRs and IPI doorbells are shared between
threads in a core. In per-thread mode, supervisor and user state is
not shared between threads.

OpenPOWER systems after POWER8 use LPAR per thread mode, and it is
required for KVM. Enterprise systems use LPAR per core mode, as they
partition the machine by core.

Implement a lpar-per-core machine option for powernv machines. This
is fixed true for POWER8 machines, and defaults off for P9 and P10.

With this change, powernv8 SMT now works sufficiently to run Linux,
with a single socket. Multi-threaded KVM guests still have problems,
as does multi-socket Linux boot.

Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
This commit is contained in:
Nicholas Piggin 2024-05-24 15:02:46 +10:00
parent c889195508
commit 3b5ea01e98
6 changed files with 52 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

38
hw/ppc/pnv.c
View File

@ -1026,6 +1026,11 @@ static void pnv_init(MachineState *machine)
exit(1);
}
/* Set lpar-per-core mode if lpar-per-thread is not supported */
if (!pmc->has_lpar_per_thread) {
pnv->lpar_per_core = true;
}
pnv->num_chips =
machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads);
@ -1102,6 +1107,8 @@ static void pnv_init(MachineState *machine)
&error_fatal);
object_property_set_bool(chip, "big-core", pnv->big_core,
&error_fatal);
object_property_set_bool(chip, "lpar-per-core", pnv->lpar_per_core,
&error_fatal);
/*
* The POWER8 machine use the XICS interrupt interface.
* Propagate the XICS fabric to the chip and its controllers.
@ -2338,6 +2345,8 @@ static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
&error_fatal);
object_property_set_bool(OBJECT(pnv_core), "quirk-tb-big-core",
pmc->quirk_tb_big_core, &error_fatal);
object_property_set_bool(OBJECT(pnv_core), "lpar-per-core",
chip->lpar_per_core, &error_fatal);
object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip),
&error_abort);
@ -2373,6 +2382,7 @@ static Property pnv_chip_properties[] = {
DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0),
DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1),
DEFINE_PROP_BOOL("big-core", PnvChip, big_core, false),
DEFINE_PROP_BOOL("lpar-per-core", PnvChip, lpar_per_core, false),
DEFINE_PROP_END_OF_LIST(),
};
@ -2593,6 +2603,18 @@ static void pnv_machine_set_big_core(Object *obj, bool value, Error **errp)
pnv->big_core = value;
}
static bool pnv_machine_get_lpar_per_core(Object *obj, Error **errp)
{
PnvMachineState *pnv = PNV_MACHINE(obj);
return pnv->lpar_per_core;
}
static void pnv_machine_set_lpar_per_core(Object *obj, bool value, Error **errp)
{
PnvMachineState *pnv = PNV_MACHINE(obj);
pnv->lpar_per_core = value;
}
static bool pnv_machine_get_hb(Object *obj, Error **errp)
{
PnvMachineState *pnv = PNV_MACHINE(obj);
@ -2632,6 +2654,8 @@ static void pnv_machine_power8_class_init(ObjectClass *oc, void *data)
pmc->compat = compat;
pmc->compat_size = sizeof(compat);
pmc->max_smt_threads = 8;
/* POWER8 is always lpar-per-core mode */
pmc->has_lpar_per_thread = false;
machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB);
}
@ -2657,6 +2681,7 @@ static void pnv_machine_power9_class_init(ObjectClass *oc, void *data)
pmc->compat = compat;
pmc->compat_size = sizeof(compat);
pmc->max_smt_threads = 4;
pmc->has_lpar_per_thread = true;
pmc->dt_power_mgt = pnv_dt_power_mgt;
machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB);
@ -2666,6 +2691,12 @@ static void pnv_machine_power9_class_init(ObjectClass *oc, void *data)
pnv_machine_set_big_core);
object_class_property_set_description(oc, "big-core",
"Use big-core (aka fused-core) mode");
object_class_property_add_bool(oc, "lpar-per-core",
pnv_machine_get_lpar_per_core,
pnv_machine_set_lpar_per_core);
object_class_property_set_description(oc, "lpar-per-core",
"Use 1 LPAR per core mode");
}
static void pnv_machine_p10_common_class_init(ObjectClass *oc, void *data)
@ -2688,6 +2719,7 @@ static void pnv_machine_p10_common_class_init(ObjectClass *oc, void *data)
pmc->compat = compat;
pmc->compat_size = sizeof(compat);
pmc->max_smt_threads = 4;
pmc->has_lpar_per_thread = true;
pmc->quirk_tb_big_core = true;
pmc->dt_power_mgt = pnv_dt_power_mgt;
@ -2713,6 +2745,12 @@ static void pnv_machine_power10_class_init(ObjectClass *oc, void *data)
pnv_machine_set_big_core);
object_class_property_set_description(oc, "big-core",
"Use big-core (aka fused-core) mode");
object_class_property_add_bool(oc, "lpar-per-core",
pnv_machine_get_lpar_per_core,
pnv_machine_set_lpar_per_core);
object_class_property_set_description(oc, "lpar-per-core",
"Use 1 LPAR per core mode");
}
static void pnv_machine_p10_rainier_class_init(ObjectClass *oc, void *data)

8
hw/ppc/pnv_core.c
View File

@ -208,6 +208,9 @@ static uint64_t pnv_core_power10_xscom_read(void *opaque, hwaddr addr,
val |= PPC_BIT(56 + i);
}
}
if (pc->lpar_per_core) {
val |= PPC_BIT(62);
}
break;
case PNV10_XSCOM_EC_CORE_THREAD_INFO:
break;
@ -321,6 +324,10 @@ static void pnv_core_cpu_realize(PnvCore *pc, PowerPCCPU *cpu, Error **errp,
env->core_index = core_hwid;
}
if (pc->lpar_per_core) {
cpu_ppc_set_1lpar(cpu);
}
/* Set time-base frequency to 512 MHz */
cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ);
}
@ -427,6 +434,7 @@ static Property pnv_core_properties[] = {
DEFINE_PROP_BOOL("big-core", PnvCore, big_core, false),
DEFINE_PROP_BOOL("quirk-tb-big-core", PnvCore, tod_state.big_core_quirk,
false),
DEFINE_PROP_BOOL("lpar-per-core", PnvCore, lpar_per_core, false),
DEFINE_PROP_LINK("chip", PnvCore, chip, TYPE_PNV_CHIP, PnvChip *),
DEFINE_PROP_END_OF_LIST(),
};

2
include/hw/ppc/pnv.h
View File

@ -77,6 +77,7 @@ struct PnvMachineClass {
const char *compat;
int compat_size;
int max_smt_threads;
bool has_lpar_per_thread;
bool quirk_tb_big_core;
void (*dt_power_mgt)(PnvMachineState *pnv, void *fdt);
@ -104,6 +105,7 @@ struct PnvMachineState {
hwaddr fw_load_addr;
bool big_core;
bool lpar_per_core;
};
PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id);

1
include/hw/ppc/pnv_chip.h
View File

@ -28,6 +28,7 @@ struct PnvChip {
uint64_t ram_size;
bool big_core;
bool lpar_per_core;
uint32_t nr_cores;
uint32_t nr_threads;
uint64_t cores_mask;

1
include/hw/ppc/pnv_core.h
View File

@ -57,6 +57,7 @@ struct PnvCore {
/*< public >*/
PowerPCCPU **threads;
bool big_core;
bool lpar_per_core;
uint32_t pir;
uint32_t hwid;
uint64_t hrmor;

3
target/ppc/cpu_init.c
View File

@ -6786,7 +6786,8 @@ void cpu_ppc_set_1lpar(PowerPCCPU *cpu)
/*
* pseries SMT means "LPAR per core" mode, e.g., msgsndp is usable
* between threads.
* between threads. powernv be in either mode, and it mostly affects
* supervisor visible registers and instructions.
*/
if (env->flags & POWERPC_FLAG_SMT) {
env->flags |= POWERPC_FLAG_SMT_1LPAR;