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target/riscv: Support the version for ss1p13 

Add RISC-V privilege 1.13 support.

Signed-off-by: Fea.Wang <fea.wang@sifive.com>
Signed-off-by: Fea.Wang <fea.wang@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liwei1518@gmail.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20240606135454.119186-7-fea.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Fea.Wang 2024-06-06 21:54:54 +08:00 committed by Alistair Francis
parent 8392a7c148
commit 3adf4def19
2 changed files with 9 additions and 1 deletions
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6
target/riscv/cpu.c
View File

@ -1779,7 +1779,9 @@ static int priv_spec_from_str(const char *priv_spec_str)
{
int priv_version = -1;
if (!g_strcmp0(priv_spec_str, PRIV_VER_1_12_0_STR)) {
if (!g_strcmp0(priv_spec_str, PRIV_VER_1_13_0_STR)) {
priv_version = PRIV_VERSION_1_13_0;
} else if (!g_strcmp0(priv_spec_str, PRIV_VER_1_12_0_STR)) {
priv_version = PRIV_VERSION_1_12_0;
} else if (!g_strcmp0(priv_spec_str, PRIV_VER_1_11_0_STR)) {
priv_version = PRIV_VERSION_1_11_0;
@ -1799,6 +1801,8 @@ const char *priv_spec_to_str(int priv_version)
return PRIV_VER_1_11_0_STR;
case PRIV_VERSION_1_12_0:
return PRIV_VER_1_12_0_STR;
case PRIV_VERSION_1_13_0:
return PRIV_VER_1_13_0_STR;
default:
return NULL;
}

4
target/riscv/tcg/tcg-cpu.c
View File

@ -318,6 +318,10 @@ static void riscv_cpu_update_named_features(RISCVCPU *cpu)
cpu->cfg.has_priv_1_12 = true;
}
if (cpu->env.priv_ver >= PRIV_VERSION_1_13_0) {
cpu->cfg.has_priv_1_13 = true;
}
/* zic64b is 1.12 or later */
cpu->cfg.ext_zic64b = cpu->cfg.cbom_blocksize == 64 &&
cpu->cfg.cbop_blocksize == 64 &&