mirror of https://github.com/xemu-project/xemu.git
tcg/ppc: Use ADDPCIS in tcg_out_tb_start
With ISA v3.0, we can use ADDPCIS instead of BCL+MFLR to load NIA. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -362,6 +362,7 @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct, int vece)
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#define CRNAND XO19(225)
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#define CROR XO19(449)
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#define CRNOR XO19( 33)
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#define ADDPCIS XO19( 2)
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#define EXTSB XO31(954)
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#define EXTSH XO31(922)
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@ -859,6 +860,19 @@ static inline void tcg_out_sari64(TCGContext *s, TCGReg dst, TCGReg src, int c)
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tcg_out32(s, SRADI | RA(dst) | RS(src) | SH(c & 0x1f) | ((c >> 4) & 2));
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}
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static void tcg_out_addpcis(TCGContext *s, TCGReg dst, intptr_t imm)
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{
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uint32_t d0, d1, d2;
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tcg_debug_assert((imm & 0xffff) == 0);
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tcg_debug_assert(imm == (int32_t)imm);
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d2 = extract32(imm, 16, 1);
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d1 = extract32(imm, 17, 5);
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d0 = extract32(imm, 22, 10);
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tcg_out32(s, ADDPCIS | RT(dst) | (d1 << 16) | (d0 << 6) | d2);
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}
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static void tcg_out_bswap16(TCGContext *s, TCGReg dst, TCGReg src, int flags)
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{
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TCGReg tmp = dst == src ? TCG_REG_R0 : dst;
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@ -2534,9 +2548,14 @@ static void tcg_out_tb_start(TCGContext *s)
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{
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/* Load TCG_REG_TB. */
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if (USE_REG_TB) {
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/* bcl 20,31,$+4 (preferred form for getting nia) */
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tcg_out32(s, BC | BO_ALWAYS | BI(7, CR_SO) | 0x4 | LK);
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tcg_out32(s, MFSPR | RT(TCG_REG_TB) | LR);
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if (have_isa_3_00) {
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/* lnia REG_TB */
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tcg_out_addpcis(s, TCG_REG_TB, 0);
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} else {
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/* bcl 20,31,$+4 (preferred form for getting nia) */
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tcg_out32(s, BC | BO_ALWAYS | BI(7, CR_SO) | 0x4 | LK);
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tcg_out32(s, MFSPR | RT(TCG_REG_TB) | LR);
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}
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}
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}
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