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target/arm: Reject add/sub w/ shifted byte early 

Remove the unparsed extractions in trans_ADD_zzi, trans_SUBR_zzi,
and do_zzi_sat which are intended to reject an 8-bit shift of an
8-bit constant for 8-bit element.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-73-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2022-05-27 11:18:25 -07:00 committed by Peter Maydell
parent c437c59ba1
commit 3a40518079
2 changed files with 28 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

35
target/arm/sve.decode
View File

@ -793,13 +793,34 @@ FDUP 00100101 esz:2 111 00 1110 imm:8 rd:5
}
# SVE integer add/subtract immediate (unpredicated)
ADD_zzi 00100101 .. 100 000 11 . ........ ..... @rdn_sh_i8u
SUB_zzi 00100101 .. 100 001 11 . ........ ..... @rdn_sh_i8u
SUBR_zzi 00100101 .. 100 011 11 . ........ ..... @rdn_sh_i8u
SQADD_zzi 00100101 .. 100 100 11 . ........ ..... @rdn_sh_i8u
UQADD_zzi 00100101 .. 100 101 11 . ........ ..... @rdn_sh_i8u
SQSUB_zzi 00100101 .. 100 110 11 . ........ ..... @rdn_sh_i8u
UQSUB_zzi 00100101 .. 100 111 11 . ........ ..... @rdn_sh_i8u
{
INVALID 00100101 00 100 000 11 1 -------- -----
ADD_zzi 00100101 .. 100 000 11 . ........ ..... @rdn_sh_i8u
}
{
INVALID 00100101 00 100 001 11 1 -------- -----
SUB_zzi 00100101 .. 100 001 11 . ........ ..... @rdn_sh_i8u
}
{
INVALID 00100101 00 100 011 11 1 -------- -----
SUBR_zzi 00100101 .. 100 011 11 . ........ ..... @rdn_sh_i8u
}
{
INVALID 00100101 00 100 100 11 1 -------- -----
SQADD_zzi 00100101 .. 100 100 11 . ........ ..... @rdn_sh_i8u
}
{
INVALID 00100101 00 100 101 11 1 -------- -----
UQADD_zzi 00100101 .. 100 101 11 . ........ ..... @rdn_sh_i8u
}
{
INVALID 00100101 00 100 110 11 1 -------- -----
SQSUB_zzi 00100101 .. 100 110 11 . ........ ..... @rdn_sh_i8u
}
{
INVALID 00100101 00 100 111 11 1 -------- -----
UQSUB_zzi 00100101 .. 100 111 11 . ........ ..... @rdn_sh_i8u
}
# SVE integer min/max immediate (unpredicated)
SMAX_zzi 00100101 .. 101 000 110 ........ ..... @rdn_i8s

9
target/arm/translate-sve.c
View File

@ -3262,9 +3262,6 @@ static bool trans_DUP_i(DisasContext *s, arg_DUP_i *a)
static bool trans_ADD_zzi(DisasContext *s, arg_rri_esz *a)
{
if (a->esz == 0 && extract32(s->insn, 13, 1)) {
return false;
}
return gen_gvec_fn_arg_zzi(s, tcg_gen_gvec_addi, a);
}
@ -3305,9 +3302,6 @@ static bool trans_SUBR_zzi(DisasContext *s, arg_rri_esz *a)
.scalar_first = true }
};
if (a->esz == 0 && extract32(s->insn, 13, 1)) {
return false;
}
if (sve_access_check(s)) {
unsigned vsz = vec_full_reg_size(s);
tcg_gen_gvec_2s(vec_full_reg_offset(s, a->rd),
@ -3321,9 +3315,6 @@ TRANS_FEAT(MUL_zzi, aa64_sve, gen_gvec_fn_arg_zzi, tcg_gen_gvec_muli, a)
static bool do_zzi_sat(DisasContext *s, arg_rri_esz *a, bool u, bool d)
{
if (a->esz == 0 && extract32(s->insn, 13, 1)) {
return false;
}
if (sve_access_check(s)) {
do_sat_addsub_vec(s, a->esz, a->rd, a->rn,
tcg_constant_i64(a->imm), u, d);