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next-cube: fix up compilation when DEBUG_NEXT is enabled 

These were accidentally introduced by my last series.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Thomas Huth <huth@tuxfamily.org>
Message-ID: <20241023085852.1061031-2-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Thomas Huth <thuth@redhat.com>
This commit is contained in:
Mark Cave-Ayland 2024-10-23 09:58:17 +01:00 committed by Thomas Huth
parent bc9da794cc
commit 39734497a3
1 changed files with 5 additions and 5 deletions
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10
hw/m68k/next-cube.c
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@ -404,7 +404,7 @@ static void next_scr_writefn(void *opaque, hwaddr addr, uint64_t val,
switch (addr) {
case 0x14108:
DPRINTF("FDCSR Write: %x\n", value);
DPRINTF("FDCSR Write: %"PRIx64 "\n", val);
if (val == 0x0) {
/* qemu_irq_raise(s->fd_irq[0]); */
}
@ -468,15 +468,15 @@ static void next_scr_writefn(void *opaque, hwaddr addr, uint64_t val,
/* int_mask |= 0x1000; */
/* s->scsi_csr_1 |= 0x80; */
}
DPRINTF("SCSICSR Write: %x\n", val);
DPRINTF("SCSICSR Write: %"PRIx64 "\n", val);
/* s->scsi_csr_1 = val; */
break;
/* Hardware timer latch - not implemented yet */
case 0x1a000:
default:
DPRINTF("BMAP Write @ 0x%x with 0x%x size %u\n", (unsigned int)addr,
val, size);
DPRINTF("BMAP Write @ 0x%x with 0x%"PRIx64 " size %u\n",
(unsigned int)addr, val, size);
}
}
@ -585,7 +585,7 @@ static void next_dma_write(void *opaque, hwaddr addr, uint64_t val,
break;
default:
DPRINTF("DMA write @ %x w/ %x\n", (unsigned)addr, (unsigned)value);
DPRINTF("DMA write @ %x w/ %x\n", (unsigned)addr, (unsigned)val);
}
}