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target/riscv: machine: Add debug state description
Add a subsection to machine.c to migrate debug CSR state. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220421003324.1134983-5-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -216,7 +216,38 @@ static const VMStateDescription vmstate_kvmtimer = {
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VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU),
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VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU),
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VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU),
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VMSTATE_END_OF_LIST()
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}
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};
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static bool debug_needed(void *opaque)
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{
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RISCVCPU *cpu = opaque;
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CPURISCVState *env = &cpu->env;
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return riscv_feature(env, RISCV_FEATURE_DEBUG);
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}
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static const VMStateDescription vmstate_debug_type2 = {
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.name = "cpu/debug/type2",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINTTL(mcontrol, type2_trigger_t),
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VMSTATE_UINTTL(maddress, type2_trigger_t),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_debug = {
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.name = "cpu/debug",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = debug_needed,
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.fields = (VMStateField[]) {
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VMSTATE_UINTTL(env.trigger_cur, RISCVCPU),
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VMSTATE_STRUCT_ARRAY(env.type2_trig, RISCVCPU, TRIGGER_TYPE2_NUM,
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0, vmstate_debug_type2, type2_trigger_t),
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VMSTATE_END_OF_LIST()
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}
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};
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@ -315,6 +346,7 @@ const VMStateDescription vmstate_riscv_cpu = {
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&vmstate_rv128,
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&vmstate_kvmtimer,
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&vmstate_envcfg,
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&vmstate_debug,
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NULL
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}
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};
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