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target/riscv: Reorg sum check in get_physical_address 

Implement this by adjusting prot, which reduces the set of
checks required.  This prevents exec to be set for U pages
in MMUIdx_S_SUM.  While it had been technically incorrect,
it did not manifest as a bug, because we will never attempt
to execute from MMUIdx_S_SUM.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-26-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-26-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Richard Henderson 2023-04-12 13:43:33 +02:00 committed by Alistair Francis
parent e1dd15076b
commit 38303e8a2c
1 changed files with 11 additions and 11 deletions
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22
target/riscv/cpu_helper.c
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@ -786,7 +786,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
*ret_prot = 0;
hwaddr base;
int levels, ptidxbits, ptesize, vm, sum, widened;
int levels, ptidxbits, ptesize, vm, widened;
if (first_stage == true) {
if (use_background) {
@ -817,7 +817,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
}
widened = 2;
}
sum = mmuidx_sum(mmu_idx);
switch (vm) {
case VM_1_10_SV32:
levels = 2; ptidxbits = 10; ptesize = 4; break;
@ -985,15 +985,15 @@ restart:
prot |= PAGE_EXEC;
}
if ((pte & PTE_U) &&
((mode != PRV_U) && (!sum || access_type == MMU_INST_FETCH))) {
/*
* User PTE flags when not U mode and mstatus.SUM is not set,
* or the access type is an instruction fetch.
*/
return TRANSLATE_FAIL;
}
if (!(pte & PTE_U) && (mode != PRV_S)) {
if (pte & PTE_U) {
if (mode != PRV_U) {
if (!mmuidx_sum(mmu_idx)) {
return TRANSLATE_FAIL;
}
/* SUM allows only read+write, not execute. */
prot &= PAGE_READ | PAGE_WRITE;
}
} else if (mode != PRV_S) {
/* Supervisor PTE flags when not S mode */
return TRANSLATE_FAIL;
}