From 37e79058031b0490734f724edf4e1691f6b3601e Mon Sep 17 00:00:00 2001 From: Weiwei Li Date: Wed, 17 May 2023 17:15:14 +0800 Subject: [PATCH] target/riscv: Flush TLB when MMWP or MML bits are changed MMWP and MML bits may affect the allowed privs of PMP entries and the default privs, both of which may change the allowed privs of exsited TLB entries. So we need flush TLB when they are changed. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Message-Id: <20230517091519.34439-8-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/pmp.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 2403039133..4d62dfc732 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -578,6 +578,9 @@ void mseccfg_csr_write(CPURISCVState *env, target_ulong val) if (riscv_cpu_cfg(env)->epmp) { /* Sticky bits */ val |= (env->mseccfg & (MSECCFG_MMWP | MSECCFG_MML)); + if ((val ^ env->mseccfg) & (MSECCFG_MMWP | MSECCFG_MML)) { + tlb_flush(env_cpu(env)); + } } else { val &= ~(MSECCFG_MMWP | MSECCFG_MML | MSECCFG_RLB); }