mirror of https://github.com/xemu-project/xemu.git
macio: move heathrow PIC inside macio-oldworld device
The heathrow PIC is located within the macio device on real hardware so make it a child of the macio-oldworld device. This also removes the need for setting and checking a separate PIC object property link on the macio-oldworld device which currently causes the automated QOM introspection tests to fail. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20201229175619.6051-4-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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49ac51ae80
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370022ce31
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@ -140,7 +140,7 @@ static void macio_oldworld_realize(PCIDevice *d, Error **errp)
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{
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{
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MacIOState *s = MACIO(d);
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MacIOState *s = MACIO(d);
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OldWorldMacIOState *os = OLDWORLD_MACIO(d);
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OldWorldMacIOState *os = OLDWORLD_MACIO(d);
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DeviceState *pic_dev = DEVICE(os->pic);
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DeviceState *pic_dev = DEVICE(&os->pic);
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Error *err = NULL;
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Error *err = NULL;
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SysBusDevice *sysbus_dev;
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SysBusDevice *sysbus_dev;
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@ -150,6 +150,14 @@ static void macio_oldworld_realize(PCIDevice *d, Error **errp)
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return;
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return;
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}
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}
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/* Heathrow PIC */
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if (!qdev_realize(DEVICE(&os->pic), BUS(&s->macio_bus), errp)) {
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return;
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}
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sysbus_dev = SYS_BUS_DEVICE(&os->pic);
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memory_region_add_subregion(&s->bar, 0x0,
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sysbus_mmio_get_region(sysbus_dev, 0));
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qdev_prop_set_uint64(DEVICE(&s->cuda), "timebase-frequency",
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qdev_prop_set_uint64(DEVICE(&s->cuda), "timebase-frequency",
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s->frequency);
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s->frequency);
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if (!qdev_realize(DEVICE(&s->cuda), BUS(&s->macio_bus), errp)) {
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if (!qdev_realize(DEVICE(&s->cuda), BUS(&s->macio_bus), errp)) {
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@ -175,11 +183,6 @@ static void macio_oldworld_realize(PCIDevice *d, Error **errp)
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sysbus_mmio_get_region(sysbus_dev, 0));
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sysbus_mmio_get_region(sysbus_dev, 0));
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pmac_format_nvram_partition(&os->nvram, os->nvram.size);
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pmac_format_nvram_partition(&os->nvram, os->nvram.size);
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/* Heathrow PIC */
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sysbus_dev = SYS_BUS_DEVICE(os->pic);
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memory_region_add_subregion(&s->bar, 0x0,
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sysbus_mmio_get_region(sysbus_dev, 0));
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/* IDE buses */
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/* IDE buses */
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macio_realize_ide(s, &os->ide[0],
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macio_realize_ide(s, &os->ide[0],
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qdev_get_gpio_in(pic_dev, OLDWORLD_IDE0_IRQ),
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qdev_get_gpio_in(pic_dev, OLDWORLD_IDE0_IRQ),
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@ -218,10 +221,7 @@ static void macio_oldworld_init(Object *obj)
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DeviceState *dev;
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DeviceState *dev;
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int i;
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int i;
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object_property_add_link(obj, "pic", TYPE_HEATHROW,
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object_initialize_child(OBJECT(s), "pic", &os->pic, TYPE_HEATHROW);
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(Object **) &os->pic,
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qdev_prop_allow_set_link_before_realize,
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0);
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object_initialize_child(OBJECT(s), "cuda", &s->cuda, TYPE_CUDA);
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object_initialize_child(OBJECT(s), "cuda", &s->cuda, TYPE_CUDA);
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@ -98,7 +98,7 @@ static void ppc_heathrow_init(MachineState *machine)
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MACIOIDEState *macio_ide;
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MACIOIDEState *macio_ide;
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ESCCState *escc;
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ESCCState *escc;
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SysBusDevice *s;
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SysBusDevice *s;
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DeviceState *dev, *pic_dev;
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DeviceState *dev, *pic_dev, *grackle_dev;
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BusState *adb_bus;
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BusState *adb_bus;
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uint64_t bios_addr;
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uint64_t bios_addr;
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int bios_size;
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int bios_size;
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@ -227,10 +227,17 @@ static void ppc_heathrow_init(MachineState *machine)
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}
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}
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}
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}
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/* Timebase Frequency */
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if (kvm_enabled()) {
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tbfreq = kvmppc_get_tbfreq();
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} else {
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tbfreq = TBFREQ;
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}
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/* Grackle PCI host bridge */
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/* Grackle PCI host bridge */
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dev = qdev_new(TYPE_GRACKLE_PCI_HOST_BRIDGE);
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grackle_dev = qdev_new(TYPE_GRACKLE_PCI_HOST_BRIDGE);
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qdev_prop_set_uint32(dev, "ofw-addr", 0x80000000);
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qdev_prop_set_uint32(grackle_dev, "ofw-addr", 0x80000000);
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s = SYS_BUS_DEVICE(dev);
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s = SYS_BUS_DEVICE(grackle_dev);
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sysbus_realize_and_unref(s, &error_fatal);
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sysbus_realize_and_unref(s, &error_fatal);
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sysbus_mmio_map(s, 0, GRACKLE_BASE);
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sysbus_mmio_map(s, 0, GRACKLE_BASE);
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@ -242,14 +249,30 @@ static void ppc_heathrow_init(MachineState *machine)
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memory_region_add_subregion(get_system_memory(), 0xfe000000,
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memory_region_add_subregion(get_system_memory(), 0xfe000000,
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sysbus_mmio_get_region(s, 3));
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sysbus_mmio_get_region(s, 3));
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/* XXX: we register only 1 output pin for heathrow PIC */
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pci_bus = PCI_HOST_BRIDGE(grackle_dev)->bus;
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pic_dev = qdev_new(TYPE_HEATHROW);
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sysbus_realize_and_unref(SYS_BUS_DEVICE(pic_dev), &error_fatal);
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/* MacIO */
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macio = pci_new(PCI_DEVFN(16, 0), TYPE_OLDWORLD_MACIO);
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dev = DEVICE(macio);
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qdev_prop_set_uint64(dev, "frequency", tbfreq);
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escc = ESCC(object_resolve_path_component(OBJECT(macio), "escc"));
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qdev_prop_set_chr(DEVICE(escc), "chrA", serial_hd(0));
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qdev_prop_set_chr(DEVICE(escc), "chrB", serial_hd(1));
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pci_realize_and_unref(macio, pci_bus, &error_fatal);
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pic_dev = DEVICE(object_resolve_path_component(OBJECT(macio), "pic"));
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for (i = 0; i < 4; i++) {
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qdev_connect_gpio_out(grackle_dev, i,
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qdev_get_gpio_in(pic_dev, 0x15 + i));
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}
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/* Connect the heathrow PIC outputs to the 6xx bus */
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/* Connect the heathrow PIC outputs to the 6xx bus */
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for (i = 0; i < smp_cpus; i++) {
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for (i = 0; i < smp_cpus; i++) {
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switch (PPC_INPUT(env)) {
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switch (PPC_INPUT(env)) {
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case PPC_FLAGS_INPUT_6xx:
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case PPC_FLAGS_INPUT_6xx:
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/* XXX: we register only 1 output pin for heathrow PIC */
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qdev_connect_gpio_out(pic_dev, 0,
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qdev_connect_gpio_out(pic_dev, 0,
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((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]);
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((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]);
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break;
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break;
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@ -259,40 +282,14 @@ static void ppc_heathrow_init(MachineState *machine)
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}
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}
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}
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}
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/* Timebase Frequency */
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if (kvm_enabled()) {
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tbfreq = kvmppc_get_tbfreq();
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} else {
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tbfreq = TBFREQ;
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}
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for (i = 0; i < 4; i++) {
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qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(pic_dev, 0x15 + i));
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}
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pci_bus = PCI_HOST_BRIDGE(dev)->bus;
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pci_vga_init(pci_bus);
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pci_vga_init(pci_bus);
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for (i = 0; i < nb_nics; i++) {
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for (i = 0; i < nb_nics; i++) {
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pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL);
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pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL);
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}
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}
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/* MacIO IDE */
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ide_drive_get(hd, ARRAY_SIZE(hd));
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ide_drive_get(hd, ARRAY_SIZE(hd));
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/* MacIO */
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macio = pci_new(PCI_DEVFN(16, 0), TYPE_OLDWORLD_MACIO);
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dev = DEVICE(macio);
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qdev_prop_set_uint64(dev, "frequency", tbfreq);
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object_property_set_link(OBJECT(macio), "pic", OBJECT(pic_dev),
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&error_abort);
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escc = ESCC(object_resolve_path_component(OBJECT(macio), "escc"));
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qdev_prop_set_chr(DEVICE(escc), "chrA", serial_hd(0));
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qdev_prop_set_chr(DEVICE(escc), "chrB", serial_hd(1));
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pci_realize_and_unref(macio, pci_bus, &error_fatal);
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macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
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macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
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"ide[0]"));
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"ide[0]"));
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macio_ide_init_drives(macio_ide, hd);
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macio_ide_init_drives(macio_ide, hd);
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@ -301,6 +298,7 @@ static void ppc_heathrow_init(MachineState *machine)
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"ide[1]"));
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"ide[1]"));
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macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]);
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macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]);
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/* MacIO CUDA/ADB */
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dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda"));
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dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda"));
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adb_bus = qdev_get_child_bus(dev, "adb.0");
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adb_bus = qdev_get_child_bus(dev, "adb.0");
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dev = qdev_new(TYPE_ADB_KEYBOARD);
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dev = qdev_new(TYPE_ADB_KEYBOARD);
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@ -99,7 +99,7 @@ struct OldWorldMacIOState {
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MacIOState parent_obj;
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MacIOState parent_obj;
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/*< public >*/
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/*< public >*/
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HeathrowState *pic;
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HeathrowState pic;
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MacIONVRAMState nvram;
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MacIONVRAMState nvram;
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MACIOIDEState ide[2];
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MACIOIDEState ide[2];
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