mirror of https://github.com/xemu-project/xemu.git
target/sparc: Drop get_temp_i32
Translators are no longer required to free tcg temporaries, therefore there's no need to record temps for later freeing. Replace the few uses with tcg_temp_new_i32. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -84,8 +84,6 @@ typedef struct DisasContext {
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uint32_t cc_op; /* current CC operation */
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sparc_def_t *def;
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TCGv_i32 t32[3];
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int n_t32;
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#ifdef TARGET_SPARC64
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int fprs_dirty;
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int asi;
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@ -129,14 +127,6 @@ static int sign_extend(int x, int len)
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#define IS_IMM (insn & (1<<13))
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static inline TCGv_i32 get_temp_i32(DisasContext *dc)
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{
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TCGv_i32 t;
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assert(dc->n_t32 < ARRAY_SIZE(dc->t32));
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dc->t32[dc->n_t32++] = t = tcg_temp_new_i32();
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return t;
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}
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static inline void gen_update_fprs_dirty(DisasContext *dc, int rd)
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{
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#if defined(TARGET_SPARC64)
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@ -153,7 +143,7 @@ static inline void gen_update_fprs_dirty(DisasContext *dc, int rd)
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/* floating point registers moves */
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static TCGv_i32 gen_load_fpr_F(DisasContext *dc, unsigned int src)
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{
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TCGv_i32 ret = get_temp_i32(dc);
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TCGv_i32 ret = tcg_temp_new_i32();
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if (src & 1) {
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tcg_gen_extrl_i64_i32(ret, cpu_fpr[src / 2]);
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} else {
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@ -175,7 +165,7 @@ static void gen_store_fpr_F(DisasContext *dc, unsigned int dst, TCGv_i32 v)
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static TCGv_i32 gen_dest_fpr_F(DisasContext *dc)
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{
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return get_temp_i32(dc);
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return tcg_temp_new_i32();
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}
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static TCGv_i64 gen_load_fpr_D(DisasContext *dc, unsigned int src)
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@ -5516,7 +5506,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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break;
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}
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#endif
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cpu_dst_32 = get_temp_i32(dc);
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cpu_dst_32 = tcg_temp_new_i32();
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tcg_gen_qemu_ld_i32(cpu_dst_32, cpu_addr,
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dc->mem_idx, MO_TEUL);
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gen_helper_ldfsr(cpu_fsr, cpu_env, cpu_fsr, cpu_dst_32);
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@ -5763,13 +5753,6 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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goto egress;
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#endif
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egress:
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if (dc->n_t32 != 0) {
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int i;
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for (i = dc->n_t32 - 1; i >= 0; --i) {
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tcg_temp_free_i32(dc->t32[i]);
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}
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dc->n_t32 = 0;
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}
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}
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static void sparc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
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