mirror of https://github.com/xemu-project/xemu.git
kill dsp_core
This commit is contained in:
espes
parent
8d029a7c2e
commit
35e0ab7e69
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@ -1 +1 @@
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obj-y += dsp.o dsp_core.o dsp_cpu.o dsp_disasm.o
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obj-y += dsp.o dsp_cpu.o dsp_disasm.o
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@ -26,7 +26,7 @@
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#include "dsp_cpu.h"
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#include "dsp_disasm.h"
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#include "dsp_core.h"
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#include "dsp_int.h"
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#include "dsp.h"
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@ -34,12 +34,7 @@
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#define BITMASK(x) ((1<<(x))-1)
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#define ARRAYSIZE(x) (int)(sizeof(x)/sizeof(x[0]))
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#define DEBUG 0
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#if DEBUG
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#define DPRINTF(a) printf a
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#else
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#define DPRINTF(a)
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#endif
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#define DPRINTF(s, ...) fprintf(stderr, s, ## __VA_ARGS__)
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static int32_t save_cycles;
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@ -80,9 +75,9 @@ void dsp_reset(void)
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/**
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* Run DSP for certain cycles
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*/
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void dsp_run(int nHostCycles)
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void dsp_run(int cycles)
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{
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save_cycles += nHostCycles * 2;
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save_cycles += cycles;
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if (dsp_core.running == 0) return;
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@ -455,3 +450,82 @@ bool dsp_disasm_set_register(const char *arg, uint32_t value)
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}
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return false;
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}
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/*--- the DSP core itself ---*/
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dsp_core_t dsp_core;
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static void (*dsp_host_interrupt)(void); /* Function to trigger host interrupt */
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/* Init DSP emulation */
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void dsp_core_init(void (*host_interrupt)(void))
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{
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DPRINTF("Dsp: core init\n");
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dsp_host_interrupt = host_interrupt;
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memset(&dsp_core, 0, sizeof(dsp_core_t));
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}
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/* Shutdown DSP emulation */
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void dsp_core_shutdown(void)
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{
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dsp_core.running = 0;
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DPRINTF("Dsp: core shutdown\n");
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}
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/* Reset */
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void dsp_core_reset(void)
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{
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int i;
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DPRINTF("Dsp: core reset\n");
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dsp_core_shutdown();
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/* Memory */
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memset(dsp_core.periph, 0, sizeof(dsp_core.periph));
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memset(dsp_core.stack, 0, sizeof(dsp_core.stack));
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memset(dsp_core.registers, 0, sizeof(dsp_core.registers));
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// dsp_core.dsp_host_rtx = 0;
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// dsp_core.dsp_host_htx = 0;
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/* Registers */
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dsp_core.pc = 0x0000;
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dsp_core.registers[DSP_REG_OMR]=0x02;
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for (i=0;i<8;i++) {
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dsp_core.registers[DSP_REG_M0+i]=0x00ffff;
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}
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/* Interruptions */
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memset((void*)dsp_core.interrupt_isPending, 0, sizeof(dsp_core.interrupt_isPending));
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dsp_core.interrupt_state = DSP_INTERRUPT_NONE;
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dsp_core.interrupt_instr_fetch = -1;
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dsp_core.interrupt_save_pc = -1;
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dsp_core.interrupt_counter = 0;
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dsp_core.interrupt_pipeline_count = 0;
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for (i=0;i<5;i++) {
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dsp_core.interrupt_ipl[i] = 3;
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}
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for (i=5;i<12;i++) {
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dsp_core.interrupt_ipl[i] = -1;
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}
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/* Other hardware registers */
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// dsp_core.periph[DSP_SPACE_X][DSP_IPR]=0;
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// dsp_core.periph[DSP_SPACE_X][DSP_BCR]=0xffff;
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/* Misc */
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dsp_core.loop_rep = 0;
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DPRINTF("Dsp: reset done\n");
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dsp56k_init_cpu();
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}
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@ -33,6 +33,12 @@ void dsp_uninit(void);
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void dsp_reset(void);
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void dsp_run(int nHostCycles);
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/* Emulator call these to init/stop/reset DSP emulation */
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void dsp_core_init(void (*host_interrupt)(void));
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void dsp_core_shutdown(void);
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void dsp_core_reset(void);
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/* Dsp Debugger commands */
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uint32_t dsp_get_pc(void);
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uint32_t dsp_get_next_pc(uint32_t pc);
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@ -1,101 +0,0 @@
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/*
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DSP56300 emulation
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Based on Hatari DSP M56001 emulation
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(C) 2003-2008 ARAnyM developer team
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <stdio.h>
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#include <string.h>
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#include <math.h>
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#include "dsp.h"
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#include "dsp_cpu.h"
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#include "dsp_core.h"
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/*--- the DSP core itself ---*/
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dsp_core_t dsp_core;
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static void (*dsp_host_interrupt)(void); /* Function to trigger host interrupt */
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#define DPRINTF(s, ...) fprintf(stderr, s, ## __VA_ARGS__)
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/* Init DSP emulation */
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void dsp_core_init(void (*host_interrupt)(void))
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{
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DPRINTF("Dsp: core init\n");
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dsp_host_interrupt = host_interrupt;
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memset(&dsp_core, 0, sizeof(dsp_core_t));
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}
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/* Shutdown DSP emulation */
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void dsp_core_shutdown(void)
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{
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dsp_core.running = 0;
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DPRINTF("Dsp: core shutdown\n");
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}
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/* Reset */
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void dsp_core_reset(void)
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{
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int i;
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DPRINTF("Dsp: core reset\n");
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dsp_core_shutdown();
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/* Memory */
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memset(dsp_core.periph, 0, sizeof(dsp_core.periph));
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memset(dsp_core.stack, 0, sizeof(dsp_core.stack));
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memset(dsp_core.registers, 0, sizeof(dsp_core.registers));
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// dsp_core.dsp_host_rtx = 0;
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// dsp_core.dsp_host_htx = 0;
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/* Registers */
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dsp_core.pc = 0x0000;
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dsp_core.registers[DSP_REG_OMR]=0x02;
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for (i=0;i<8;i++) {
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dsp_core.registers[DSP_REG_M0+i]=0x00ffff;
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}
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/* Interruptions */
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memset((void*)dsp_core.interrupt_isPending, 0, sizeof(dsp_core.interrupt_isPending));
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dsp_core.interrupt_state = DSP_INTERRUPT_NONE;
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dsp_core.interrupt_instr_fetch = -1;
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dsp_core.interrupt_save_pc = -1;
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dsp_core.interrupt_counter = 0;
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dsp_core.interrupt_pipeline_count = 0;
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for (i=0;i<5;i++) {
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dsp_core.interrupt_ipl[i] = 3;
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}
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for (i=5;i<12;i++) {
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dsp_core.interrupt_ipl[i] = -1;
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}
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/* Other hardware registers */
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// dsp_core.periph[DSP_SPACE_X][DSP_IPR]=0;
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// dsp_core.periph[DSP_SPACE_X][DSP_BCR]=0xffff;
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/* Misc */
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dsp_core.loop_rep = 0;
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DPRINTF("Dsp: reset done\n");
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dsp56k_init_cpu();
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}
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@ -1,103 +0,0 @@
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/*
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DSP56300 emulation
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Based on Hatari DSP M56001 emulation
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(C) 2003-2008 ARAnyM developer team
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef DSP_CORE_H
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#define DSP_CORE_H
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#include <stdint.h>
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#include "dsp_cpu.h"
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#define DSP_INTERRUPT_NONE 0x0
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#define DSP_INTERRUPT_DISABLED 0x1
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#define DSP_INTERRUPT_LONG 0x2
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#define DSP_INTER_RESET 0x0
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#define DSP_INTER_ILLEGAL 0x1
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#define DSP_INTER_STACK_ERROR 0x2
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#define DSP_INTER_TRACE 0x3
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#define DSP_INTER_SWI 0x4
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#define DSP_INTER_HOST_COMMAND 0x5
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#define DSP_INTER_HOST_RCV_DATA 0x6
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#define DSP_INTER_HOST_TRX_DATA 0x7
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#define DSP_INTER_SSI_RCV_DATA_E 0x8
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#define DSP_INTER_SSI_RCV_DATA 0x9
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#define DSP_INTER_SSI_TRX_DATA_E 0xa
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#define DSP_INTER_SSI_TRX_DATA 0xb
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typedef struct dsp_core_s dsp_core_t;
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typedef struct dsp_interrupt_s dsp_interrupt_t;
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struct dsp_interrupt_s {
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const uint16_t inter;
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const uint16_t vectorAddr;
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const uint16_t periph;
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const char *name;
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};
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struct dsp_core_s {
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/* DSP executing instructions ? */
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int running;
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/* DSP instruction Cycle counter */
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uint16_t instr_cycle;
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/* Registers */
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uint32_t pc;
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uint32_t registers[DSP_REG_MAX];
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/* stack[0=ssh], stack[1=ssl] */
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uint32_t stack[2][16];
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uint32_t xram[DSP_XRAM_SIZE];
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uint32_t yram[DSP_YRAM_SIZE];
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uint32_t pram[DSP_PRAM_SIZE];
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/* peripheral space, x:0xffff80-0xffffff */
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uint32_t periph[DSP_PERIPH_SIZE];
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/* Misc */
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uint32_t loop_rep; /* executing rep ? */
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uint32_t pc_on_rep; /* True if PC is on REP instruction */
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/* Interruptions */
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uint16_t interrupt_state; /* NONE, FAST or LONG interrupt */
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uint16_t interrupt_instr_fetch; /* vector of the current interrupt */
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uint16_t interrupt_save_pc; /* save next pc value before interrupt */
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uint16_t interrupt_counter; /* count number of pending interrupts */
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uint16_t interrupt_IplToRaise; /* save the IPL level to save in the SR register */
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uint16_t interrupt_pipeline_count; /* used to prefetch correctly the 2 inter instructions */
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int16_t interrupt_ipl[12]; /* store the current IPL for each interrupt */
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uint16_t interrupt_isPending[12]; /* store if interrupt is pending for each interrupt */
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};
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/* DSP */
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extern dsp_core_t dsp_core;
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/* Emulator call these to init/stop/reset DSP emulation */
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void dsp_core_init(void (*host_interrupt)(void));
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void dsp_core_shutdown(void);
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void dsp_core_reset(void);
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#endif /* DSP_CORE_H */
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@ -23,9 +23,10 @@
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#include <string.h>
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#include <assert.h>
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#include "dsp_core.h"
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#include "dsp_cpu.h"
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#include "dsp_disasm.h"
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#include "dsp_int.h"
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#include "dsp_cpu.h"
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#define TRACE_DSP_DISASM 1
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#define TRACE_DSP_DISASM_REG 1
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@ -25,96 +25,6 @@
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#include <stdio.h>
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#include <stdint.h>
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#define DSP_OMR_MA 0x00
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#define DSP_OMR_MB 0x01
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#define DSP_OMR_DE 0x02
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#define DSP_OMR_SD 0x06
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#define DSP_OMR_EA 0x07
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#define DSP_SR_C 0x00
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#define DSP_SR_V 0x01
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#define DSP_SR_Z 0x02
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#define DSP_SR_N 0x03
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#define DSP_SR_U 0x04
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#define DSP_SR_E 0x05
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#define DSP_SR_L 0x06
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#define DSP_SR_I0 0x08
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#define DSP_SR_I1 0x09
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#define DSP_SR_S0 0x0a
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#define DSP_SR_S1 0x0b
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#define DSP_SR_T 0x0d
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#define DSP_SR_LF 0x0f
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#define DSP_SP_SE 0x04
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#define DSP_SP_UF 0x05
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/* Registers numbers in dsp.registers[] */
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#define DSP_REG_X0 0x04
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#define DSP_REG_X1 0x05
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#define DSP_REG_Y0 0x06
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#define DSP_REG_Y1 0x07
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#define DSP_REG_A0 0x08
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#define DSP_REG_B0 0x09
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#define DSP_REG_A2 0x0a
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#define DSP_REG_B2 0x0b
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#define DSP_REG_A1 0x0c
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#define DSP_REG_B1 0x0d
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#define DSP_REG_A 0x0e
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#define DSP_REG_B 0x0f
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#define DSP_REG_R0 0x10
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#define DSP_REG_R1 0x11
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#define DSP_REG_R2 0x12
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#define DSP_REG_R3 0x13
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#define DSP_REG_R4 0x14
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#define DSP_REG_R5 0x15
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#define DSP_REG_R6 0x16
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#define DSP_REG_R7 0x17
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#define DSP_REG_N0 0x18
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#define DSP_REG_N1 0x19
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#define DSP_REG_N2 0x1a
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#define DSP_REG_N3 0x1b
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#define DSP_REG_N4 0x1c
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#define DSP_REG_N5 0x1d
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#define DSP_REG_N6 0x1e
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#define DSP_REG_N7 0x1f
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#define DSP_REG_M0 0x20
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#define DSP_REG_M1 0x21
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#define DSP_REG_M2 0x22
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#define DSP_REG_M3 0x23
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#define DSP_REG_M4 0x24
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#define DSP_REG_M5 0x25
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#define DSP_REG_M6 0x26
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#define DSP_REG_M7 0x27
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#define DSP_REG_SR 0x39
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#define DSP_REG_OMR 0x3a
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#define DSP_REG_SP 0x3b
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#define DSP_REG_SSH 0x3c
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#define DSP_REG_SSL 0x3d
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#define DSP_REG_LA 0x3e
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#define DSP_REG_LC 0x3f
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#define DSP_REG_NULL 0x00
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#define DSP_REG_LCSAVE 0x30
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#define DSP_REG_MAX 0x40
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/* Memory spaces for dsp.ram[], dsp.rom[] */
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#define DSP_SPACE_X 0x00
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#define DSP_SPACE_Y 0x01
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#define DSP_SPACE_P 0x02
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#define DSP_XRAM_SIZE 4096
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#define DSP_YRAM_SIZE 2048
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#define DSP_PRAM_SIZE 4096
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#define DSP_PERIPH_BASE 0xFFFF80
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#define DSP_PERIPH_SIZE 128
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/* Functions */
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void dsp56k_init_cpu(void); /* Set dsp_core to use */
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void dsp56k_execute_instruction(void); /* Execute 1 instruction */
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@ -24,11 +24,10 @@
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#include <string.h>
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#include <inttypes.h>
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#include "dsp_core.h"
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#include "dsp_cpu.h"
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#include "dsp_int.h"
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#include "dsp_disasm.h"
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/* More disasm infos, if wanted */
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#define DSP_DISASM_REG_PC 0
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@ -22,6 +22,8 @@
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#ifndef DSP_DISASM_H
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#define DSP_DISASM_H
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#include <stdint.h>
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typedef enum {
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DSP_TRACE_MODE,
|
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DSP_DISASM_MODE
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|
|
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@ -0,0 +1,164 @@
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#ifndef DSP_INT_H
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#define DSP_INT_H
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#include <stdint.h>
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|
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#define DSP_OMR_MA 0x00
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#define DSP_OMR_MB 0x01
|
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#define DSP_OMR_DE 0x02
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#define DSP_OMR_SD 0x06
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#define DSP_OMR_EA 0x07
|
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|
||||
#define DSP_SR_C 0x00
|
||||
#define DSP_SR_V 0x01
|
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#define DSP_SR_Z 0x02
|
||||
#define DSP_SR_N 0x03
|
||||
#define DSP_SR_U 0x04
|
||||
#define DSP_SR_E 0x05
|
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#define DSP_SR_L 0x06
|
||||
|
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#define DSP_SR_I0 0x08
|
||||
#define DSP_SR_I1 0x09
|
||||
#define DSP_SR_S0 0x0a
|
||||
#define DSP_SR_S1 0x0b
|
||||
#define DSP_SR_T 0x0d
|
||||
#define DSP_SR_LF 0x0f
|
||||
|
||||
#define DSP_SP_SE 0x04
|
||||
#define DSP_SP_UF 0x05
|
||||
|
||||
/* Registers numbers in dsp.registers[] */
|
||||
#define DSP_REG_X0 0x04
|
||||
#define DSP_REG_X1 0x05
|
||||
#define DSP_REG_Y0 0x06
|
||||
#define DSP_REG_Y1 0x07
|
||||
#define DSP_REG_A0 0x08
|
||||
#define DSP_REG_B0 0x09
|
||||
#define DSP_REG_A2 0x0a
|
||||
#define DSP_REG_B2 0x0b
|
||||
#define DSP_REG_A1 0x0c
|
||||
#define DSP_REG_B1 0x0d
|
||||
#define DSP_REG_A 0x0e
|
||||
#define DSP_REG_B 0x0f
|
||||
|
||||
#define DSP_REG_R0 0x10
|
||||
#define DSP_REG_R1 0x11
|
||||
#define DSP_REG_R2 0x12
|
||||
#define DSP_REG_R3 0x13
|
||||
#define DSP_REG_R4 0x14
|
||||
#define DSP_REG_R5 0x15
|
||||
#define DSP_REG_R6 0x16
|
||||
#define DSP_REG_R7 0x17
|
||||
|
||||
#define DSP_REG_N0 0x18
|
||||
#define DSP_REG_N1 0x19
|
||||
#define DSP_REG_N2 0x1a
|
||||
#define DSP_REG_N3 0x1b
|
||||
#define DSP_REG_N4 0x1c
|
||||
#define DSP_REG_N5 0x1d
|
||||
#define DSP_REG_N6 0x1e
|
||||
#define DSP_REG_N7 0x1f
|
||||
|
||||
#define DSP_REG_M0 0x20
|
||||
#define DSP_REG_M1 0x21
|
||||
#define DSP_REG_M2 0x22
|
||||
#define DSP_REG_M3 0x23
|
||||
#define DSP_REG_M4 0x24
|
||||
#define DSP_REG_M5 0x25
|
||||
#define DSP_REG_M6 0x26
|
||||
#define DSP_REG_M7 0x27
|
||||
|
||||
#define DSP_REG_SR 0x39
|
||||
#define DSP_REG_OMR 0x3a
|
||||
#define DSP_REG_SP 0x3b
|
||||
#define DSP_REG_SSH 0x3c
|
||||
#define DSP_REG_SSL 0x3d
|
||||
#define DSP_REG_LA 0x3e
|
||||
#define DSP_REG_LC 0x3f
|
||||
|
||||
#define DSP_REG_NULL 0x00
|
||||
#define DSP_REG_LCSAVE 0x30
|
||||
|
||||
#define DSP_REG_MAX 0x40
|
||||
|
||||
/* Memory spaces for dsp.ram[], dsp.rom[] */
|
||||
#define DSP_SPACE_X 0x00
|
||||
#define DSP_SPACE_Y 0x01
|
||||
#define DSP_SPACE_P 0x02
|
||||
|
||||
#define DSP_XRAM_SIZE 4096
|
||||
#define DSP_YRAM_SIZE 2048
|
||||
#define DSP_PRAM_SIZE 4096
|
||||
|
||||
#define DSP_PERIPH_BASE 0xFFFF80
|
||||
#define DSP_PERIPH_SIZE 128
|
||||
|
||||
|
||||
|
||||
|
||||
#define DSP_INTERRUPT_NONE 0x0
|
||||
#define DSP_INTERRUPT_DISABLED 0x1
|
||||
#define DSP_INTERRUPT_LONG 0x2
|
||||
|
||||
#define DSP_INTER_RESET 0x0
|
||||
#define DSP_INTER_ILLEGAL 0x1
|
||||
#define DSP_INTER_STACK_ERROR 0x2
|
||||
#define DSP_INTER_TRACE 0x3
|
||||
#define DSP_INTER_SWI 0x4
|
||||
#define DSP_INTER_HOST_COMMAND 0x5
|
||||
#define DSP_INTER_HOST_RCV_DATA 0x6
|
||||
#define DSP_INTER_HOST_TRX_DATA 0x7
|
||||
#define DSP_INTER_SSI_RCV_DATA_E 0x8
|
||||
#define DSP_INTER_SSI_RCV_DATA 0x9
|
||||
#define DSP_INTER_SSI_TRX_DATA_E 0xa
|
||||
#define DSP_INTER_SSI_TRX_DATA 0xb
|
||||
|
||||
|
||||
typedef struct dsp_interrupt_s {
|
||||
const uint16_t inter;
|
||||
const uint16_t vectorAddr;
|
||||
const uint16_t periph;
|
||||
const char *name;
|
||||
} dsp_interrupt_t;
|
||||
|
||||
typedef struct dsp_core_s {
|
||||
|
||||
/* DSP executing instructions ? */
|
||||
int running;
|
||||
|
||||
/* DSP instruction Cycle counter */
|
||||
uint16_t instr_cycle;
|
||||
|
||||
/* Registers */
|
||||
uint32_t pc;
|
||||
uint32_t registers[DSP_REG_MAX];
|
||||
|
||||
/* stack[0=ssh], stack[1=ssl] */
|
||||
uint32_t stack[2][16];
|
||||
|
||||
uint32_t xram[DSP_XRAM_SIZE];
|
||||
uint32_t yram[DSP_YRAM_SIZE];
|
||||
uint32_t pram[DSP_PRAM_SIZE];
|
||||
|
||||
/* peripheral space, x:0xffff80-0xffffff */
|
||||
uint32_t periph[DSP_PERIPH_SIZE];
|
||||
|
||||
/* Misc */
|
||||
uint32_t loop_rep; /* executing rep ? */
|
||||
uint32_t pc_on_rep; /* True if PC is on REP instruction */
|
||||
|
||||
/* Interruptions */
|
||||
uint16_t interrupt_state; /* NONE, FAST or LONG interrupt */
|
||||
uint16_t interrupt_instr_fetch; /* vector of the current interrupt */
|
||||
uint16_t interrupt_save_pc; /* save next pc value before interrupt */
|
||||
uint16_t interrupt_counter; /* count number of pending interrupts */
|
||||
uint16_t interrupt_IplToRaise; /* save the IPL level to save in the SR register */
|
||||
uint16_t interrupt_pipeline_count; /* used to prefetch correctly the 2 inter instructions */
|
||||
int16_t interrupt_ipl[12]; /* store the current IPL for each interrupt */
|
||||
uint16_t interrupt_isPending[12]; /* store if interrupt is pending for each interrupt */
|
||||
} dsp_core_t;
|
||||
|
||||
/* DSP */
|
||||
extern dsp_core_t dsp_core;
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue