mirror of https://github.com/xemu-project/xemu.git
target/openrisc: Implement EVBAR register
Exception Vector Base Address Register (EVBAR) - This optional register can be used to apply an offset to the exception vector addresses. The significant bits (31-12) of the vector offset address for each exception depend on the setting of the Supervision Register (SR)'s EPH bit and the Exception Vector Base Address Register (EVBAR). Its presence is indicated by the EVBARP bit in the CPU Configuration Register (CPUCFGR). Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com> Signed-off-by: Stafford Horne <shorne@gmail.com>
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@ -134,6 +134,7 @@ static void or1200_initfn(Object *obj)
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set_feature(cpu, OPENRISC_FEATURE_OB32S);
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set_feature(cpu, OPENRISC_FEATURE_OF32S);
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set_feature(cpu, OPENRISC_FEATURE_EVBAR);
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}
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static void openrisc_any_initfn(Object *obj)
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@ -141,6 +142,7 @@ static void openrisc_any_initfn(Object *obj)
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OpenRISCCPU *cpu = OPENRISC_CPU(obj);
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set_feature(cpu, OPENRISC_FEATURE_OB32S);
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set_feature(cpu, OPENRISC_FEATURE_EVBAR);
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}
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typedef struct OpenRISCCPUInfo {
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@ -111,6 +111,11 @@ enum {
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CPUCFGR_OF32S = (1 << 7),
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CPUCFGR_OF64S = (1 << 8),
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CPUCFGR_OV64S = (1 << 9),
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/* CPUCFGR_ND = (1 << 10), */
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/* CPUCFGR_AVRP = (1 << 11), */
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CPUCFGR_EVBARP = (1 << 12),
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/* CPUCFGR_ISRP = (1 << 13), */
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/* CPUCFGR_AECSRP = (1 << 14), */
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};
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/* DMMU configure register */
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@ -200,6 +205,7 @@ enum {
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OPENRISC_FEATURE_OF32S = (1 << 7),
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OPENRISC_FEATURE_OF64S = (1 << 8),
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OPENRISC_FEATURE_OV64S = (1 << 9),
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OPENRISC_FEATURE_EVBAR = (1 << 12),
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};
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/* Tick Timer Mode Register */
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@ -289,6 +295,7 @@ typedef struct CPUOpenRISCState {
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uint32_t dmmucfgr; /* DMMU configure register */
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uint32_t immucfgr; /* IMMU configure register */
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uint32_t esr; /* Exception supervisor register */
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uint32_t evbar; /* Exception vector base address register */
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uint32_t fpcsr; /* Float register */
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float_status fp_status;
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@ -65,7 +65,11 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
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env->lock_addr = -1;
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if (cs->exception_index > 0 && cs->exception_index < EXCP_NR) {
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env->pc = (cs->exception_index << 8);
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hwaddr vect_pc = cs->exception_index << 8;
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if (env->cpucfgr & CPUCFGR_EVBARP) {
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vect_pc |= env->evbar;
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}
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env->pc = vect_pc;
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} else {
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cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
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}
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@ -39,6 +39,10 @@ void HELPER(mtspr)(CPUOpenRISCState *env,
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env->vr = rb;
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break;
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case TO_SPR(0, 11): /* EVBAR */
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env->evbar = rb;
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break;
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case TO_SPR(0, 16): /* NPC */
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cpu_restore_state(cs, GETPC());
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/* ??? Mirror or1ksim in not trashing delayed branch state
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@ -206,6 +210,9 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env,
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case TO_SPR(0, 4): /* IMMUCFGR */
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return env->immucfgr;
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case TO_SPR(0, 11): /* EVBAR */
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return env->evbar;
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case TO_SPR(0, 16): /* NPC (equals PC) */
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cpu_restore_state(cs, GETPC());
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return env->pc;
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