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target/hppa: Decode d for cmpclr instructions 

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-09-16 20:40:23 -07:00
parent af24075333
commit 345aa35f15
2 changed files with 9 additions and 8 deletions
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6
target/hppa/insns.decode
View File

@ -64,6 +64,7 @@
&rrr_cf_d t r1 r2 cf d
&rrr_cf_sh t r1 r2 cf sh
&rri_cf t r i cf
&rri_cf_d t r i cf d
&rrb_c_f disp n c f r1 r2
&rib_c_f disp n c f r i
@ -78,6 +79,7 @@
@rrr_cf_sh ...... r2:5 r1:5 cf:4 .... sh:2 . t:5 &rrr_cf_sh
@rrr_cf_sh0 ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf_sh sh=0
@rri_cf ...... r:5 t:5 cf:4 . ........... &rri_cf i=%lowsign_11
@rri_cf_d ...... r:5 t:5 cf:4 d:1 ........... &rri_cf_d i=%lowsign_11
@rrb_cf ...... r2:5 r1:5 c:3 ........... n:1 . \
&rrb_c_f disp=%assemble_12
@ -158,7 +160,7 @@ or 000010 ..... ..... .... 001001 . ..... @rrr_cf_d
xor 000010 ..... ..... .... 001010 . ..... @rrr_cf_d
uxor 000010 ..... ..... .... 001110 . ..... @rrr_cf_d
ds 000010 ..... ..... .... 010001 0 ..... @rrr_cf
cmpclr 000010 ..... ..... .... 100010 0 ..... @rrr_cf
cmpclr 000010 ..... ..... .... 100010 . ..... @rrr_cf_d
uaddcm 000010 ..... ..... .... 100110 . ..... @rrr_cf_d
uaddcm_tc 000010 ..... ..... .... 100111 . ..... @rrr_cf_d
dcor 000010 ..... 00000 .... 101110 . ..... @rr_cf_d
@ -189,7 +191,7 @@ addi_tc_tsv 101100 ..... ..... .... 1 ........... @rri_cf
subi 100101 ..... ..... .... 0 ........... @rri_cf
subi_tsv 100101 ..... ..... .... 1 ........... @rri_cf
cmpiclr 100100 ..... ..... .... 0 ........... @rri_cf
cmpiclr 100100 ..... ..... .... . ........... @rri_cf_d
####
# Index Mem

11
target/hppa/translate.c
View File

@ -1377,11 +1377,10 @@ static bool do_sub_imm(DisasContext *ctx, arg_rri_cf *a, bool is_tsv)
}
static void do_cmpclr(DisasContext *ctx, unsigned rt, TCGv_reg in1,
TCGv_reg in2, unsigned cf)
TCGv_reg in2, unsigned cf, bool d)
{
TCGv_reg dest, sv;
DisasCond cond;
bool d = false;
dest = tcg_temp_new();
tcg_gen_sub_reg(dest, in1, in2);
@ -2758,7 +2757,7 @@ static bool trans_xor(DisasContext *ctx, arg_rrr_cf_d *a)
return do_log_reg(ctx, a, tcg_gen_xor_reg);
}
static bool trans_cmpclr(DisasContext *ctx, arg_rrr_cf *a)
static bool trans_cmpclr(DisasContext *ctx, arg_rrr_cf_d *a)
{
TCGv_reg tcg_r1, tcg_r2;
@ -2767,7 +2766,7 @@ static bool trans_cmpclr(DisasContext *ctx, arg_rrr_cf *a)
}
tcg_r1 = load_gpr(ctx, a->r1);
tcg_r2 = load_gpr(ctx, a->r2);
do_cmpclr(ctx, a->t, tcg_r1, tcg_r2, a->cf);
do_cmpclr(ctx, a->t, tcg_r1, tcg_r2, a->cf, a->d);
return nullify_end(ctx);
}
@ -2925,7 +2924,7 @@ static bool trans_subi_tsv(DisasContext *ctx, arg_rri_cf *a)
return do_sub_imm(ctx, a, true);
}
static bool trans_cmpiclr(DisasContext *ctx, arg_rri_cf *a)
static bool trans_cmpiclr(DisasContext *ctx, arg_rri_cf_d *a)
{
TCGv_reg tcg_im, tcg_r2;
@ -2935,7 +2934,7 @@ static bool trans_cmpiclr(DisasContext *ctx, arg_rri_cf *a)
tcg_im = tcg_constant_reg(a->i);
tcg_r2 = load_gpr(ctx, a->r);
do_cmpclr(ctx, a->t, tcg_im, tcg_r2, a->cf);
do_cmpclr(ctx, a->t, tcg_im, tcg_r2, a->cf, a->d);
return nullify_end(ctx);
}