mirror of https://github.com/xemu-project/xemu.git
target/riscv: Add multi extension implied rules
Add multi extension implied rules to enable the implied extensions of the multi extension recursively. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com> Tested-by: Max Chou <max.chou@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240625114629.27793-5-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Frank Chang
Alistair Francis
parent
171773391a
commit
340c3ca5f2
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@ -2297,12 +2297,352 @@ static RISCVCPUImpliedExtsRule RVV_IMPLIED = {
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},
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};
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static RISCVCPUImpliedExtsRule ZCB_IMPLIED = {
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.ext = CPU_CFG_OFFSET(ext_zcb),
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.implied_multi_exts = {
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CPU_CFG_OFFSET(ext_zca),
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RISCV_IMPLIED_EXTS_RULE_END
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},
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};
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static RISCVCPUImpliedExtsRule ZCD_IMPLIED = {
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.ext = CPU_CFG_OFFSET(ext_zcd),
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.implied_misa_exts = RVD,
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.implied_multi_exts = {
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CPU_CFG_OFFSET(ext_zca),
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RISCV_IMPLIED_EXTS_RULE_END
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},
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};
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static RISCVCPUImpliedExtsRule ZCE_IMPLIED = {
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.ext = CPU_CFG_OFFSET(ext_zce),
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.implied_multi_exts = {
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CPU_CFG_OFFSET(ext_zcb), CPU_CFG_OFFSET(ext_zcmp),
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CPU_CFG_OFFSET(ext_zcmt),
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RISCV_IMPLIED_EXTS_RULE_END
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},
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};
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static RISCVCPUImpliedExtsRule ZCF_IMPLIED = {
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.ext = CPU_CFG_OFFSET(ext_zcf),
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.implied_misa_exts = RVF,
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.implied_multi_exts = {
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CPU_CFG_OFFSET(ext_zca),
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RISCV_IMPLIED_EXTS_RULE_END
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},
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};
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static RISCVCPUImpliedExtsRule ZCMP_IMPLIED = {
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.ext = CPU_CFG_OFFSET(ext_zcmp),
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.implied_multi_exts = {
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CPU_CFG_OFFSET(ext_zca),
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RISCV_IMPLIED_EXTS_RULE_END
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},
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};
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static RISCVCPUImpliedExtsRule ZCMT_IMPLIED = {
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.ext = CPU_CFG_OFFSET(ext_zcmt),
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.implied_multi_exts = {
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CPU_CFG_OFFSET(ext_zca), CPU_CFG_OFFSET(ext_zicsr),
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RISCV_IMPLIED_EXTS_RULE_END
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},
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};
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static RISCVCPUImpliedExtsRule ZDINX_IMPLIED = {
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.ext = CPU_CFG_OFFSET(ext_zdinx),
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.implied_multi_exts = {
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CPU_CFG_OFFSET(ext_zfinx),
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RISCV_IMPLIED_EXTS_RULE_END
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},
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};
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static RISCVCPUImpliedExtsRule ZFA_IMPLIED = {
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.ext = CPU_CFG_OFFSET(ext_zfa),
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.implied_misa_exts = RVF,
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.implied_multi_exts = { RISCV_IMPLIED_EXTS_RULE_END },
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};
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static RISCVCPUImpliedExtsRule ZFBFMIN_IMPLIED = {
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.ext = CPU_CFG_OFFSET(ext_zfbfmin),
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.implied_misa_exts = RVF,
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.implied_multi_exts = { RISCV_IMPLIED_EXTS_RULE_END },
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};
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static RISCVCPUImpliedExtsRule ZFH_IMPLIED = {
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.ext = CPU_CFG_OFFSET(ext_zfh),
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.implied_multi_exts = {
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CPU_CFG_OFFSET(ext_zfhmin),
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RISCV_IMPLIED_EXTS_RULE_END
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},
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};
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static RISCVCPUImpliedExtsRule ZFHMIN_IMPLIED = {
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.ext = CPU_CFG_OFFSET(ext_zfhmin),
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.implied_misa_exts = RVF,
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.implied_multi_exts = { RISCV_IMPLIED_EXTS_RULE_END },
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};
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static RISCVCPUImpliedExtsRule ZFINX_IMPLIED = {
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.ext = CPU_CFG_OFFSET(ext_zfinx),
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.implied_multi_exts = {
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CPU_CFG_OFFSET(ext_zicsr),
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RISCV_IMPLIED_EXTS_RULE_END
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},
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};
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static RISCVCPUImpliedExtsRule ZHINX_IMPLIED = {
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.ext = CPU_CFG_OFFSET(ext_zhinx),
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.implied_multi_exts = {
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CPU_CFG_OFFSET(ext_zhinxmin),
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RISCV_IMPLIED_EXTS_RULE_END
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},
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};
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static RISCVCPUImpliedExtsRule ZHINXMIN_IMPLIED = {
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.ext = CPU_CFG_OFFSET(ext_zhinxmin),
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.implied_multi_exts = {
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CPU_CFG_OFFSET(ext_zfinx),
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RISCV_IMPLIED_EXTS_RULE_END
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},
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};
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static RISCVCPUImpliedExtsRule ZICNTR_IMPLIED = {
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.ext = CPU_CFG_OFFSET(ext_zicntr),
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.implied_multi_exts = {
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CPU_CFG_OFFSET(ext_zicsr),
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RISCV_IMPLIED_EXTS_RULE_END
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},
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};
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static RISCVCPUImpliedExtsRule ZIHPM_IMPLIED = {
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.ext = CPU_CFG_OFFSET(ext_zihpm),
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.implied_multi_exts = {
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CPU_CFG_OFFSET(ext_zicsr),
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RISCV_IMPLIED_EXTS_RULE_END
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},
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};
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static RISCVCPUImpliedExtsRule ZK_IMPLIED = {
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.ext = CPU_CFG_OFFSET(ext_zk),
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.implied_multi_exts = {
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CPU_CFG_OFFSET(ext_zkn), CPU_CFG_OFFSET(ext_zkr),
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CPU_CFG_OFFSET(ext_zkt),
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RISCV_IMPLIED_EXTS_RULE_END
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},
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};
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static RISCVCPUImpliedExtsRule ZKN_IMPLIED = {
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.ext = CPU_CFG_OFFSET(ext_zkn),
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.implied_multi_exts = {
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CPU_CFG_OFFSET(ext_zbkb), CPU_CFG_OFFSET(ext_zbkc),
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CPU_CFG_OFFSET(ext_zbkx), CPU_CFG_OFFSET(ext_zkne),
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CPU_CFG_OFFSET(ext_zknd), CPU_CFG_OFFSET(ext_zknh),
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RISCV_IMPLIED_EXTS_RULE_END
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},
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};
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static RISCVCPUImpliedExtsRule ZKS_IMPLIED = {
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.ext = CPU_CFG_OFFSET(ext_zks),
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.implied_multi_exts = {
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CPU_CFG_OFFSET(ext_zbkb), CPU_CFG_OFFSET(ext_zbkc),
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CPU_CFG_OFFSET(ext_zbkx), CPU_CFG_OFFSET(ext_zksed),
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CPU_CFG_OFFSET(ext_zksh),
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RISCV_IMPLIED_EXTS_RULE_END
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},
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};
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static RISCVCPUImpliedExtsRule ZVBB_IMPLIED = {
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.ext = CPU_CFG_OFFSET(ext_zvbb),
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.implied_multi_exts = {
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CPU_CFG_OFFSET(ext_zvkb),
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RISCV_IMPLIED_EXTS_RULE_END
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},
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};
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static RISCVCPUImpliedExtsRule ZVE32F_IMPLIED = {
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.ext = CPU_CFG_OFFSET(ext_zve32f),
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.implied_misa_exts = RVF,
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.implied_multi_exts = {
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CPU_CFG_OFFSET(ext_zve32x),
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RISCV_IMPLIED_EXTS_RULE_END
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},
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};
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static RISCVCPUImpliedExtsRule ZVE32X_IMPLIED = {
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.ext = CPU_CFG_OFFSET(ext_zve32x),
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.implied_multi_exts = {
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CPU_CFG_OFFSET(ext_zicsr),
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RISCV_IMPLIED_EXTS_RULE_END
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},
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};
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static RISCVCPUImpliedExtsRule ZVE64D_IMPLIED = {
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.ext = CPU_CFG_OFFSET(ext_zve64d),
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.implied_misa_exts = RVD,
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.implied_multi_exts = {
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CPU_CFG_OFFSET(ext_zve64f),
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RISCV_IMPLIED_EXTS_RULE_END
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},
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};
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static RISCVCPUImpliedExtsRule ZVE64F_IMPLIED = {
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.ext = CPU_CFG_OFFSET(ext_zve64f),
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.implied_misa_exts = RVF,
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.implied_multi_exts = {
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CPU_CFG_OFFSET(ext_zve32f), CPU_CFG_OFFSET(ext_zve64x),
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RISCV_IMPLIED_EXTS_RULE_END
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},
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};
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static RISCVCPUImpliedExtsRule ZVE64X_IMPLIED = {
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.ext = CPU_CFG_OFFSET(ext_zve64x),
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.implied_multi_exts = {
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CPU_CFG_OFFSET(ext_zve32x),
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RISCV_IMPLIED_EXTS_RULE_END
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},
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};
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static RISCVCPUImpliedExtsRule ZVFBFMIN_IMPLIED = {
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.ext = CPU_CFG_OFFSET(ext_zvfbfmin),
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.implied_multi_exts = {
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CPU_CFG_OFFSET(ext_zve32f),
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RISCV_IMPLIED_EXTS_RULE_END
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},
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};
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static RISCVCPUImpliedExtsRule ZVFBFWMA_IMPLIED = {
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.ext = CPU_CFG_OFFSET(ext_zvfbfwma),
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.implied_multi_exts = {
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CPU_CFG_OFFSET(ext_zvfbfmin), CPU_CFG_OFFSET(ext_zfbfmin),
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RISCV_IMPLIED_EXTS_RULE_END
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},
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};
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static RISCVCPUImpliedExtsRule ZVFH_IMPLIED = {
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.ext = CPU_CFG_OFFSET(ext_zvfh),
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.implied_multi_exts = {
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CPU_CFG_OFFSET(ext_zvfhmin), CPU_CFG_OFFSET(ext_zfhmin),
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RISCV_IMPLIED_EXTS_RULE_END
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},
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};
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static RISCVCPUImpliedExtsRule ZVFHMIN_IMPLIED = {
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.ext = CPU_CFG_OFFSET(ext_zvfhmin),
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.implied_multi_exts = {
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CPU_CFG_OFFSET(ext_zve32f),
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RISCV_IMPLIED_EXTS_RULE_END
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},
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};
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static RISCVCPUImpliedExtsRule ZVKN_IMPLIED = {
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.ext = CPU_CFG_OFFSET(ext_zvkn),
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.implied_multi_exts = {
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CPU_CFG_OFFSET(ext_zvkned), CPU_CFG_OFFSET(ext_zvknhb),
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CPU_CFG_OFFSET(ext_zvkb), CPU_CFG_OFFSET(ext_zvkt),
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RISCV_IMPLIED_EXTS_RULE_END
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},
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};
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static RISCVCPUImpliedExtsRule ZVKNC_IMPLIED = {
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.ext = CPU_CFG_OFFSET(ext_zvknc),
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.implied_multi_exts = {
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CPU_CFG_OFFSET(ext_zvkn), CPU_CFG_OFFSET(ext_zvbc),
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RISCV_IMPLIED_EXTS_RULE_END
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},
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};
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static RISCVCPUImpliedExtsRule ZVKNG_IMPLIED = {
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.ext = CPU_CFG_OFFSET(ext_zvkng),
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.implied_multi_exts = {
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CPU_CFG_OFFSET(ext_zvkn), CPU_CFG_OFFSET(ext_zvkg),
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RISCV_IMPLIED_EXTS_RULE_END
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},
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};
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static RISCVCPUImpliedExtsRule ZVKNHB_IMPLIED = {
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.ext = CPU_CFG_OFFSET(ext_zvknhb),
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.implied_multi_exts = {
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CPU_CFG_OFFSET(ext_zve64x),
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RISCV_IMPLIED_EXTS_RULE_END
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},
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};
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static RISCVCPUImpliedExtsRule ZVKS_IMPLIED = {
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.ext = CPU_CFG_OFFSET(ext_zvks),
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.implied_multi_exts = {
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CPU_CFG_OFFSET(ext_zvksed), CPU_CFG_OFFSET(ext_zvksh),
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CPU_CFG_OFFSET(ext_zvkb), CPU_CFG_OFFSET(ext_zvkt),
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RISCV_IMPLIED_EXTS_RULE_END
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},
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};
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static RISCVCPUImpliedExtsRule ZVKSC_IMPLIED = {
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.ext = CPU_CFG_OFFSET(ext_zvksc),
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.implied_multi_exts = {
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CPU_CFG_OFFSET(ext_zvks), CPU_CFG_OFFSET(ext_zvbc),
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RISCV_IMPLIED_EXTS_RULE_END
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},
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};
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static RISCVCPUImpliedExtsRule ZVKSG_IMPLIED = {
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.ext = CPU_CFG_OFFSET(ext_zvksg),
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.implied_multi_exts = {
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CPU_CFG_OFFSET(ext_zvks), CPU_CFG_OFFSET(ext_zvkg),
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RISCV_IMPLIED_EXTS_RULE_END
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},
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};
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RISCVCPUImpliedExtsRule *riscv_misa_ext_implied_rules[] = {
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&RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED,
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&RVM_IMPLIED, &RVV_IMPLIED, NULL
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};
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RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {
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&ZCB_IMPLIED, &ZCD_IMPLIED, &ZCE_IMPLIED,
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&ZCF_IMPLIED, &ZCMP_IMPLIED, &ZCMT_IMPLIED,
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&ZDINX_IMPLIED, &ZFA_IMPLIED, &ZFBFMIN_IMPLIED,
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&ZFH_IMPLIED, &ZFHMIN_IMPLIED, &ZFINX_IMPLIED,
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&ZHINX_IMPLIED, &ZHINXMIN_IMPLIED, &ZICNTR_IMPLIED,
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&ZIHPM_IMPLIED, &ZK_IMPLIED, &ZKN_IMPLIED,
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&ZKS_IMPLIED, &ZVBB_IMPLIED, &ZVE32F_IMPLIED,
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&ZVE32X_IMPLIED, &ZVE64D_IMPLIED, &ZVE64F_IMPLIED,
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&ZVE64X_IMPLIED, &ZVFBFMIN_IMPLIED, &ZVFBFWMA_IMPLIED,
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&ZVFH_IMPLIED, &ZVFHMIN_IMPLIED, &ZVKN_IMPLIED,
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&ZVKNC_IMPLIED, &ZVKNG_IMPLIED, &ZVKNHB_IMPLIED,
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&ZVKS_IMPLIED, &ZVKSC_IMPLIED, &ZVKSG_IMPLIED,
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NULL
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};
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