mirror of https://github.com/xemu-project/xemu.git
target/riscv: Introduce mmuidx_priv
Use the priv level encoded into the mmu_idx, rather than starting from env->priv. We have already checked MPRV+MPP in riscv_cpu_mmu_index -- no need to repeat that. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230325105429.1142530-14-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-14-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -758,7 +758,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
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*/
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*/
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MemTxResult res;
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MemTxResult res;
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MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
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MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
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int mode = env->priv;
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int mode = mmuidx_priv(mmu_idx);
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bool use_background = false;
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bool use_background = false;
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hwaddr ppn;
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hwaddr ppn;
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int napot_bits = 0;
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int napot_bits = 0;
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@ -781,10 +781,6 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
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*/
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*/
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if (riscv_cpu_two_stage_lookup(mmu_idx)) {
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if (riscv_cpu_two_stage_lookup(mmu_idx)) {
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mode = get_field(env->hstatus, HSTATUS_SPVP);
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mode = get_field(env->hstatus, HSTATUS_SPVP);
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} else if (mode == PRV_M && access_type != MMU_INST_FETCH) {
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if (get_field(env->mstatus, MSTATUS_MPRV)) {
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mode = get_field(env->mstatus, MSTATUS_MPP);
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}
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}
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}
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if (first_stage == false) {
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if (first_stage == false) {
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@ -37,6 +37,15 @@
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#define MMUIdx_M 3
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#define MMUIdx_M 3
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#define MMU_2STAGE_BIT (1 << 2)
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#define MMU_2STAGE_BIT (1 << 2)
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static inline int mmuidx_priv(int mmu_idx)
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{
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int ret = mmu_idx & 3;
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if (ret == MMUIdx_S_SUM) {
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ret = PRV_S;
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}
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return ret;
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}
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static inline bool mmuidx_sum(int mmu_idx)
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static inline bool mmuidx_sum(int mmu_idx)
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{
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{
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return (mmu_idx & 3) == MMUIdx_S_SUM;
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return (mmu_idx & 3) == MMUIdx_S_SUM;
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