mirror of https://github.com/xemu-project/xemu.git
target/riscv: rvv: Provide a fast path using direct access to host ram for unmasked unit-stride load/store
This commit references the sve_ldN_r/sve_stN_r helper functions in ARM target to optimize the vector unmasked unit-stride load/store implementation with following optimizations: * Get the page boundary * Probing pages/resolving host memory address at the beginning if possible * Provide new interface to direct access host memory * Switch to the original slow TLB access when cross page element/violate page permission/violate pmp/watchpoints in page The original element load/store interface is replaced by the new element load/store functions with _tlb & _host postfix that means doing the element load/store through the original softmmu flow and the direct access host memory flow. Signed-off-by: Max Chou <max.chou@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240918171412.150107-4-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Max Chou
Alistair Francis
parent
2f077842f2
commit
338aa15d50
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@ -148,34 +148,47 @@ static inline void vext_set_elem_mask(void *v0, int index,
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}
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/* elements operations for load and store */
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typedef void vext_ldst_elem_fn(CPURISCVState *env, abi_ptr addr,
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uint32_t idx, void *vd, uintptr_t retaddr);
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typedef void vext_ldst_elem_fn_tlb(CPURISCVState *env, abi_ptr addr,
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uint32_t idx, void *vd, uintptr_t retaddr);
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typedef void vext_ldst_elem_fn_host(void *vd, uint32_t idx, void *host);
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#define GEN_VEXT_LD_ELEM(NAME, ETYPE, H, LDSUF) \
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static void NAME(CPURISCVState *env, abi_ptr addr, \
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uint32_t idx, void *vd, uintptr_t retaddr)\
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{ \
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ETYPE *cur = ((ETYPE *)vd + H(idx)); \
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*cur = cpu_##LDSUF##_data_ra(env, addr, retaddr); \
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} \
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GEN_VEXT_LD_ELEM(lde_b, int8_t, H1, ldsb)
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GEN_VEXT_LD_ELEM(lde_h, int16_t, H2, ldsw)
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GEN_VEXT_LD_ELEM(lde_w, int32_t, H4, ldl)
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GEN_VEXT_LD_ELEM(lde_d, int64_t, H8, ldq)
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#define GEN_VEXT_ST_ELEM(NAME, ETYPE, H, STSUF) \
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static void NAME(CPURISCVState *env, abi_ptr addr, \
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uint32_t idx, void *vd, uintptr_t retaddr)\
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{ \
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ETYPE data = *((ETYPE *)vd + H(idx)); \
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cpu_##STSUF##_data_ra(env, addr, data, retaddr); \
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#define GEN_VEXT_LD_ELEM(NAME, ETYPE, H, LDSUF) \
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static void NAME##_tlb(CPURISCVState *env, abi_ptr addr, \
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uint32_t idx, void *vd, uintptr_t retaddr) \
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{ \
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ETYPE *cur = ((ETYPE *)vd + H(idx)); \
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*cur = cpu_##LDSUF##_data_ra(env, addr, retaddr); \
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} \
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\
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static void NAME##_host(void *vd, uint32_t idx, void *host) \
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{ \
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ETYPE *cur = ((ETYPE *)vd + H(idx)); \
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*cur = (ETYPE)LDSUF##_p(host); \
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}
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GEN_VEXT_ST_ELEM(ste_b, int8_t, H1, stb)
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GEN_VEXT_ST_ELEM(ste_h, int16_t, H2, stw)
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GEN_VEXT_ST_ELEM(ste_w, int32_t, H4, stl)
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GEN_VEXT_ST_ELEM(ste_d, int64_t, H8, stq)
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GEN_VEXT_LD_ELEM(lde_b, uint8_t, H1, ldub)
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GEN_VEXT_LD_ELEM(lde_h, uint16_t, H2, lduw)
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GEN_VEXT_LD_ELEM(lde_w, uint32_t, H4, ldl)
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GEN_VEXT_LD_ELEM(lde_d, uint64_t, H8, ldq)
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#define GEN_VEXT_ST_ELEM(NAME, ETYPE, H, STSUF) \
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static void NAME##_tlb(CPURISCVState *env, abi_ptr addr, \
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uint32_t idx, void *vd, uintptr_t retaddr) \
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{ \
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ETYPE data = *((ETYPE *)vd + H(idx)); \
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cpu_##STSUF##_data_ra(env, addr, data, retaddr); \
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} \
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\
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static void NAME##_host(void *vd, uint32_t idx, void *host) \
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{ \
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ETYPE data = *((ETYPE *)vd + H(idx)); \
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STSUF##_p(host, data); \
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}
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GEN_VEXT_ST_ELEM(ste_b, uint8_t, H1, stb)
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GEN_VEXT_ST_ELEM(ste_h, uint16_t, H2, stw)
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GEN_VEXT_ST_ELEM(ste_w, uint32_t, H4, stl)
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GEN_VEXT_ST_ELEM(ste_d, uint64_t, H8, stq)
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static void vext_set_tail_elems_1s(target_ulong vl, void *vd,
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uint32_t desc, uint32_t nf,
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@ -198,11 +211,10 @@ static void vext_set_tail_elems_1s(target_ulong vl, void *vd,
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* stride: access vector element from strided memory
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*/
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static void
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vext_ldst_stride(void *vd, void *v0, target_ulong base,
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target_ulong stride, CPURISCVState *env,
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uint32_t desc, uint32_t vm,
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vext_ldst_elem_fn *ldst_elem,
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uint32_t log2_esz, uintptr_t ra)
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vext_ldst_stride(void *vd, void *v0, target_ulong base, target_ulong stride,
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CPURISCVState *env, uint32_t desc, uint32_t vm,
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vext_ldst_elem_fn_tlb *ldst_elem, uint32_t log2_esz,
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uintptr_t ra)
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{
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uint32_t i, k;
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uint32_t nf = vext_nf(desc);
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@ -242,10 +254,10 @@ void HELPER(NAME)(void *vd, void * v0, target_ulong base, \
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ctzl(sizeof(ETYPE)), GETPC()); \
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}
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GEN_VEXT_LD_STRIDE(vlse8_v, int8_t, lde_b)
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GEN_VEXT_LD_STRIDE(vlse16_v, int16_t, lde_h)
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GEN_VEXT_LD_STRIDE(vlse32_v, int32_t, lde_w)
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GEN_VEXT_LD_STRIDE(vlse64_v, int64_t, lde_d)
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GEN_VEXT_LD_STRIDE(vlse8_v, int8_t, lde_b_tlb)
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GEN_VEXT_LD_STRIDE(vlse16_v, int16_t, lde_h_tlb)
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GEN_VEXT_LD_STRIDE(vlse32_v, int32_t, lde_w_tlb)
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GEN_VEXT_LD_STRIDE(vlse64_v, int64_t, lde_d_tlb)
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#define GEN_VEXT_ST_STRIDE(NAME, ETYPE, STORE_FN) \
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void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
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@ -257,10 +269,10 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
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ctzl(sizeof(ETYPE)), GETPC()); \
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}
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GEN_VEXT_ST_STRIDE(vsse8_v, int8_t, ste_b)
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GEN_VEXT_ST_STRIDE(vsse16_v, int16_t, ste_h)
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GEN_VEXT_ST_STRIDE(vsse32_v, int32_t, ste_w)
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GEN_VEXT_ST_STRIDE(vsse64_v, int64_t, ste_d)
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GEN_VEXT_ST_STRIDE(vsse8_v, int8_t, ste_b_tlb)
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GEN_VEXT_ST_STRIDE(vsse16_v, int16_t, ste_h_tlb)
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GEN_VEXT_ST_STRIDE(vsse32_v, int32_t, ste_w_tlb)
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GEN_VEXT_ST_STRIDE(vsse64_v, int64_t, ste_d_tlb)
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/*
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* unit-stride: access elements stored contiguously in memory
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@ -268,31 +280,103 @@ GEN_VEXT_ST_STRIDE(vsse64_v, int64_t, ste_d)
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/* unmasked unit-stride load and store operation */
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static void
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vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
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vext_ldst_elem_fn *ldst_elem, uint32_t log2_esz, uint32_t evl,
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uintptr_t ra)
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vext_page_ldst_us(CPURISCVState *env, void *vd, target_ulong addr,
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uint32_t elems, uint32_t nf, uint32_t max_elems,
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uint32_t log2_esz, bool is_load, int mmu_index,
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vext_ldst_elem_fn_tlb *ldst_tlb,
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vext_ldst_elem_fn_host *ldst_host, uintptr_t ra)
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{
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uint32_t i, k;
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void *host;
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int i, k, flags;
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uint32_t esz = 1 << log2_esz;
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uint32_t size = (elems * nf) << log2_esz;
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uint32_t evl = env->vstart + elems;
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MMUAccessType access_type = is_load ? MMU_DATA_LOAD : MMU_DATA_STORE;
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/* Check page permission/pmp/watchpoint/etc. */
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flags = probe_access_flags(env, adjust_addr(env, addr), size, access_type,
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mmu_index, true, &host, ra);
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if (flags == 0) {
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for (i = env->vstart; i < evl; ++i) {
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k = 0;
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while (k < nf) {
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ldst_host(vd, i + k * max_elems, host);
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host += esz;
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k++;
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}
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}
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env->vstart += elems;
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} else {
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/* load bytes from guest memory */
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for (i = env->vstart; i < evl; env->vstart = ++i) {
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k = 0;
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while (k < nf) {
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ldst_tlb(env, adjust_addr(env, addr), i + k * max_elems, vd,
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ra);
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addr += esz;
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k++;
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}
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}
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}
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}
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static void
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vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
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vext_ldst_elem_fn_tlb *ldst_tlb,
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vext_ldst_elem_fn_host *ldst_host, uint32_t log2_esz,
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uint32_t evl, uintptr_t ra, bool is_load)
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{
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uint32_t k;
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target_ulong page_split, elems, addr;
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uint32_t nf = vext_nf(desc);
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uint32_t max_elems = vext_max_elems(desc, log2_esz);
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uint32_t esz = 1 << log2_esz;
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uint32_t msize = nf * esz;
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int mmu_index = riscv_env_mmu_index(env, false);
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if (env->vstart >= evl) {
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env->vstart = 0;
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return;
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}
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/* load bytes from guest memory */
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for (i = env->vstart; i < evl; env->vstart = ++i) {
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k = 0;
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while (k < nf) {
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target_ulong addr = base + ((i * nf + k) << log2_esz);
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ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, ra);
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k++;
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}
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/* Calculate the page range of first page */
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addr = base + ((env->vstart * nf) << log2_esz);
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page_split = -(addr | TARGET_PAGE_MASK);
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/* Get number of elements */
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elems = page_split / msize;
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if (unlikely(env->vstart + elems >= evl)) {
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elems = evl - env->vstart;
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}
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env->vstart = 0;
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/* Load/store elements in the first page */
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if (likely(elems)) {
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vext_page_ldst_us(env, vd, addr, elems, nf, max_elems, log2_esz,
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is_load, mmu_index, ldst_tlb, ldst_host, ra);
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}
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/* Load/store elements in the second page */
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if (unlikely(env->vstart < evl)) {
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/* Cross page element */
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if (unlikely(page_split % msize)) {
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for (k = 0; k < nf; k++) {
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addr = base + ((env->vstart * nf + k) << log2_esz);
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ldst_tlb(env, adjust_addr(env, addr),
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env->vstart + k * max_elems, vd, ra);
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}
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env->vstart++;
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}
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addr = base + ((env->vstart * nf) << log2_esz);
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/* Get number of elements of second page */
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elems = evl - env->vstart;
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/* Load/store elements in the second page */
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vext_page_ldst_us(env, vd, addr, elems, nf, max_elems, log2_esz,
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is_load, mmu_index, ldst_tlb, ldst_host, ra);
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}
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env->vstart = 0;
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vext_set_tail_elems_1s(evl, vd, desc, nf, esz, max_elems);
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}
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@ -301,47 +385,47 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
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* stride, stride = NF * sizeof (ETYPE)
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*/
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#define GEN_VEXT_LD_US(NAME, ETYPE, LOAD_FN) \
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void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \
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CPURISCVState *env, uint32_t desc) \
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{ \
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uint32_t stride = vext_nf(desc) << ctzl(sizeof(ETYPE)); \
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vext_ldst_stride(vd, v0, base, stride, env, desc, false, LOAD_FN, \
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ctzl(sizeof(ETYPE)), GETPC()); \
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} \
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\
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void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
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CPURISCVState *env, uint32_t desc) \
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{ \
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vext_ldst_us(vd, base, env, desc, LOAD_FN, \
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ctzl(sizeof(ETYPE)), env->vl, GETPC()); \
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#define GEN_VEXT_LD_US(NAME, ETYPE, LOAD_FN_TLB, LOAD_FN_HOST) \
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void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \
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CPURISCVState *env, uint32_t desc) \
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{ \
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uint32_t stride = vext_nf(desc) << ctzl(sizeof(ETYPE)); \
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vext_ldst_stride(vd, v0, base, stride, env, desc, false, \
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LOAD_FN_TLB, ctzl(sizeof(ETYPE)), GETPC()); \
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} \
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\
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void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
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CPURISCVState *env, uint32_t desc) \
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{ \
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vext_ldst_us(vd, base, env, desc, LOAD_FN_TLB, LOAD_FN_HOST, \
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ctzl(sizeof(ETYPE)), env->vl, GETPC(), true); \
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}
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GEN_VEXT_LD_US(vle8_v, int8_t, lde_b)
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GEN_VEXT_LD_US(vle16_v, int16_t, lde_h)
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GEN_VEXT_LD_US(vle32_v, int32_t, lde_w)
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GEN_VEXT_LD_US(vle64_v, int64_t, lde_d)
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GEN_VEXT_LD_US(vle8_v, int8_t, lde_b_tlb, lde_b_host)
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GEN_VEXT_LD_US(vle16_v, int16_t, lde_h_tlb, lde_h_host)
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GEN_VEXT_LD_US(vle32_v, int32_t, lde_w_tlb, lde_w_host)
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GEN_VEXT_LD_US(vle64_v, int64_t, lde_d_tlb, lde_d_host)
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#define GEN_VEXT_ST_US(NAME, ETYPE, STORE_FN) \
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#define GEN_VEXT_ST_US(NAME, ETYPE, STORE_FN_TLB, STORE_FN_HOST) \
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void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \
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CPURISCVState *env, uint32_t desc) \
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{ \
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uint32_t stride = vext_nf(desc) << ctzl(sizeof(ETYPE)); \
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vext_ldst_stride(vd, v0, base, stride, env, desc, false, STORE_FN, \
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ctzl(sizeof(ETYPE)), GETPC()); \
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vext_ldst_stride(vd, v0, base, stride, env, desc, false, \
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STORE_FN_TLB, ctzl(sizeof(ETYPE)), GETPC()); \
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} \
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\
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void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
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CPURISCVState *env, uint32_t desc) \
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{ \
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vext_ldst_us(vd, base, env, desc, STORE_FN, \
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ctzl(sizeof(ETYPE)), env->vl, GETPC()); \
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vext_ldst_us(vd, base, env, desc, STORE_FN_TLB, STORE_FN_HOST, \
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ctzl(sizeof(ETYPE)), env->vl, GETPC(), false); \
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}
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GEN_VEXT_ST_US(vse8_v, int8_t, ste_b)
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GEN_VEXT_ST_US(vse16_v, int16_t, ste_h)
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GEN_VEXT_ST_US(vse32_v, int32_t, ste_w)
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GEN_VEXT_ST_US(vse64_v, int64_t, ste_d)
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GEN_VEXT_ST_US(vse8_v, int8_t, ste_b_tlb, ste_b_host)
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GEN_VEXT_ST_US(vse16_v, int16_t, ste_h_tlb, ste_h_host)
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GEN_VEXT_ST_US(vse32_v, int32_t, ste_w_tlb, ste_w_host)
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GEN_VEXT_ST_US(vse64_v, int64_t, ste_d_tlb, ste_d_host)
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/*
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* unit stride mask load and store, EEW = 1
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@ -351,8 +435,8 @@ void HELPER(vlm_v)(void *vd, void *v0, target_ulong base,
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{
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/* evl = ceil(vl/8) */
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uint8_t evl = (env->vl + 7) >> 3;
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vext_ldst_us(vd, base, env, desc, lde_b,
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0, evl, GETPC());
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vext_ldst_us(vd, base, env, desc, lde_b_tlb, lde_b_host,
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0, evl, GETPC(), true);
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}
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void HELPER(vsm_v)(void *vd, void *v0, target_ulong base,
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@ -360,8 +444,8 @@ void HELPER(vsm_v)(void *vd, void *v0, target_ulong base,
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{
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/* evl = ceil(vl/8) */
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uint8_t evl = (env->vl + 7) >> 3;
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vext_ldst_us(vd, base, env, desc, ste_b,
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0, evl, GETPC());
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vext_ldst_us(vd, base, env, desc, ste_b_tlb, ste_b_host,
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0, evl, GETPC(), false);
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}
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/*
|
||||
|
|
@ -386,7 +470,7 @@ static inline void
|
|||
vext_ldst_index(void *vd, void *v0, target_ulong base,
|
||||
void *vs2, CPURISCVState *env, uint32_t desc,
|
||||
vext_get_index_addr get_index_addr,
|
||||
vext_ldst_elem_fn *ldst_elem,
|
||||
vext_ldst_elem_fn_tlb *ldst_elem,
|
||||
uint32_t log2_esz, uintptr_t ra)
|
||||
{
|
||||
uint32_t i, k;
|
||||
|
|
@ -427,22 +511,22 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
|
|||
LOAD_FN, ctzl(sizeof(ETYPE)), GETPC()); \
|
||||
}
|
||||
|
||||
GEN_VEXT_LD_INDEX(vlxei8_8_v, int8_t, idx_b, lde_b)
|
||||
GEN_VEXT_LD_INDEX(vlxei8_16_v, int16_t, idx_b, lde_h)
|
||||
GEN_VEXT_LD_INDEX(vlxei8_32_v, int32_t, idx_b, lde_w)
|
||||
GEN_VEXT_LD_INDEX(vlxei8_64_v, int64_t, idx_b, lde_d)
|
||||
GEN_VEXT_LD_INDEX(vlxei16_8_v, int8_t, idx_h, lde_b)
|
||||
GEN_VEXT_LD_INDEX(vlxei16_16_v, int16_t, idx_h, lde_h)
|
||||
GEN_VEXT_LD_INDEX(vlxei16_32_v, int32_t, idx_h, lde_w)
|
||||
GEN_VEXT_LD_INDEX(vlxei16_64_v, int64_t, idx_h, lde_d)
|
||||
GEN_VEXT_LD_INDEX(vlxei32_8_v, int8_t, idx_w, lde_b)
|
||||
GEN_VEXT_LD_INDEX(vlxei32_16_v, int16_t, idx_w, lde_h)
|
||||
GEN_VEXT_LD_INDEX(vlxei32_32_v, int32_t, idx_w, lde_w)
|
||||
GEN_VEXT_LD_INDEX(vlxei32_64_v, int64_t, idx_w, lde_d)
|
||||
GEN_VEXT_LD_INDEX(vlxei64_8_v, int8_t, idx_d, lde_b)
|
||||
GEN_VEXT_LD_INDEX(vlxei64_16_v, int16_t, idx_d, lde_h)
|
||||
GEN_VEXT_LD_INDEX(vlxei64_32_v, int32_t, idx_d, lde_w)
|
||||
GEN_VEXT_LD_INDEX(vlxei64_64_v, int64_t, idx_d, lde_d)
|
||||
GEN_VEXT_LD_INDEX(vlxei8_8_v, int8_t, idx_b, lde_b_tlb)
|
||||
GEN_VEXT_LD_INDEX(vlxei8_16_v, int16_t, idx_b, lde_h_tlb)
|
||||
GEN_VEXT_LD_INDEX(vlxei8_32_v, int32_t, idx_b, lde_w_tlb)
|
||||
GEN_VEXT_LD_INDEX(vlxei8_64_v, int64_t, idx_b, lde_d_tlb)
|
||||
GEN_VEXT_LD_INDEX(vlxei16_8_v, int8_t, idx_h, lde_b_tlb)
|
||||
GEN_VEXT_LD_INDEX(vlxei16_16_v, int16_t, idx_h, lde_h_tlb)
|
||||
GEN_VEXT_LD_INDEX(vlxei16_32_v, int32_t, idx_h, lde_w_tlb)
|
||||
GEN_VEXT_LD_INDEX(vlxei16_64_v, int64_t, idx_h, lde_d_tlb)
|
||||
GEN_VEXT_LD_INDEX(vlxei32_8_v, int8_t, idx_w, lde_b_tlb)
|
||||
GEN_VEXT_LD_INDEX(vlxei32_16_v, int16_t, idx_w, lde_h_tlb)
|
||||
GEN_VEXT_LD_INDEX(vlxei32_32_v, int32_t, idx_w, lde_w_tlb)
|
||||
GEN_VEXT_LD_INDEX(vlxei32_64_v, int64_t, idx_w, lde_d_tlb)
|
||||
GEN_VEXT_LD_INDEX(vlxei64_8_v, int8_t, idx_d, lde_b_tlb)
|
||||
GEN_VEXT_LD_INDEX(vlxei64_16_v, int16_t, idx_d, lde_h_tlb)
|
||||
GEN_VEXT_LD_INDEX(vlxei64_32_v, int32_t, idx_d, lde_w_tlb)
|
||||
GEN_VEXT_LD_INDEX(vlxei64_64_v, int64_t, idx_d, lde_d_tlb)
|
||||
|
||||
#define GEN_VEXT_ST_INDEX(NAME, ETYPE, INDEX_FN, STORE_FN) \
|
||||
void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
|
||||
|
|
@ -453,22 +537,22 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
|
|||
GETPC()); \
|
||||
}
|
||||
|
||||
GEN_VEXT_ST_INDEX(vsxei8_8_v, int8_t, idx_b, ste_b)
|
||||
GEN_VEXT_ST_INDEX(vsxei8_16_v, int16_t, idx_b, ste_h)
|
||||
GEN_VEXT_ST_INDEX(vsxei8_32_v, int32_t, idx_b, ste_w)
|
||||
GEN_VEXT_ST_INDEX(vsxei8_64_v, int64_t, idx_b, ste_d)
|
||||
GEN_VEXT_ST_INDEX(vsxei16_8_v, int8_t, idx_h, ste_b)
|
||||
GEN_VEXT_ST_INDEX(vsxei16_16_v, int16_t, idx_h, ste_h)
|
||||
GEN_VEXT_ST_INDEX(vsxei16_32_v, int32_t, idx_h, ste_w)
|
||||
GEN_VEXT_ST_INDEX(vsxei16_64_v, int64_t, idx_h, ste_d)
|
||||
GEN_VEXT_ST_INDEX(vsxei32_8_v, int8_t, idx_w, ste_b)
|
||||
GEN_VEXT_ST_INDEX(vsxei32_16_v, int16_t, idx_w, ste_h)
|
||||
GEN_VEXT_ST_INDEX(vsxei32_32_v, int32_t, idx_w, ste_w)
|
||||
GEN_VEXT_ST_INDEX(vsxei32_64_v, int64_t, idx_w, ste_d)
|
||||
GEN_VEXT_ST_INDEX(vsxei64_8_v, int8_t, idx_d, ste_b)
|
||||
GEN_VEXT_ST_INDEX(vsxei64_16_v, int16_t, idx_d, ste_h)
|
||||
GEN_VEXT_ST_INDEX(vsxei64_32_v, int32_t, idx_d, ste_w)
|
||||
GEN_VEXT_ST_INDEX(vsxei64_64_v, int64_t, idx_d, ste_d)
|
||||
GEN_VEXT_ST_INDEX(vsxei8_8_v, int8_t, idx_b, ste_b_tlb)
|
||||
GEN_VEXT_ST_INDEX(vsxei8_16_v, int16_t, idx_b, ste_h_tlb)
|
||||
GEN_VEXT_ST_INDEX(vsxei8_32_v, int32_t, idx_b, ste_w_tlb)
|
||||
GEN_VEXT_ST_INDEX(vsxei8_64_v, int64_t, idx_b, ste_d_tlb)
|
||||
GEN_VEXT_ST_INDEX(vsxei16_8_v, int8_t, idx_h, ste_b_tlb)
|
||||
GEN_VEXT_ST_INDEX(vsxei16_16_v, int16_t, idx_h, ste_h_tlb)
|
||||
GEN_VEXT_ST_INDEX(vsxei16_32_v, int32_t, idx_h, ste_w_tlb)
|
||||
GEN_VEXT_ST_INDEX(vsxei16_64_v, int64_t, idx_h, ste_d_tlb)
|
||||
GEN_VEXT_ST_INDEX(vsxei32_8_v, int8_t, idx_w, ste_b_tlb)
|
||||
GEN_VEXT_ST_INDEX(vsxei32_16_v, int16_t, idx_w, ste_h_tlb)
|
||||
GEN_VEXT_ST_INDEX(vsxei32_32_v, int32_t, idx_w, ste_w_tlb)
|
||||
GEN_VEXT_ST_INDEX(vsxei32_64_v, int64_t, idx_w, ste_d_tlb)
|
||||
GEN_VEXT_ST_INDEX(vsxei64_8_v, int8_t, idx_d, ste_b_tlb)
|
||||
GEN_VEXT_ST_INDEX(vsxei64_16_v, int16_t, idx_d, ste_h_tlb)
|
||||
GEN_VEXT_ST_INDEX(vsxei64_32_v, int32_t, idx_d, ste_w_tlb)
|
||||
GEN_VEXT_ST_INDEX(vsxei64_64_v, int64_t, idx_d, ste_d_tlb)
|
||||
|
||||
/*
|
||||
* unit-stride fault-only-fisrt load instructions
|
||||
|
|
@ -476,7 +560,7 @@ GEN_VEXT_ST_INDEX(vsxei64_64_v, int64_t, idx_d, ste_d)
|
|||
static inline void
|
||||
vext_ldff(void *vd, void *v0, target_ulong base,
|
||||
CPURISCVState *env, uint32_t desc,
|
||||
vext_ldst_elem_fn *ldst_elem,
|
||||
vext_ldst_elem_fn_tlb *ldst_elem,
|
||||
uint32_t log2_esz, uintptr_t ra)
|
||||
{
|
||||
uint32_t i, k, vl = 0;
|
||||
|
|
@ -562,10 +646,10 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
|
|||
ctzl(sizeof(ETYPE)), GETPC()); \
|
||||
}
|
||||
|
||||
GEN_VEXT_LDFF(vle8ff_v, int8_t, lde_b)
|
||||
GEN_VEXT_LDFF(vle16ff_v, int16_t, lde_h)
|
||||
GEN_VEXT_LDFF(vle32ff_v, int32_t, lde_w)
|
||||
GEN_VEXT_LDFF(vle64ff_v, int64_t, lde_d)
|
||||
GEN_VEXT_LDFF(vle8ff_v, int8_t, lde_b_tlb)
|
||||
GEN_VEXT_LDFF(vle16ff_v, int16_t, lde_h_tlb)
|
||||
GEN_VEXT_LDFF(vle32ff_v, int32_t, lde_w_tlb)
|
||||
GEN_VEXT_LDFF(vle64ff_v, int64_t, lde_d_tlb)
|
||||
|
||||
#define DO_SWAP(N, M) (M)
|
||||
#define DO_AND(N, M) (N & M)
|
||||
|
|
@ -582,7 +666,8 @@ GEN_VEXT_LDFF(vle64ff_v, int64_t, lde_d)
|
|||
*/
|
||||
static void
|
||||
vext_ldst_whole(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
|
||||
vext_ldst_elem_fn *ldst_elem, uint32_t log2_esz, uintptr_t ra)
|
||||
vext_ldst_elem_fn_tlb *ldst_elem, uint32_t log2_esz,
|
||||
uintptr_t ra)
|
||||
{
|
||||
uint32_t i, k, off, pos;
|
||||
uint32_t nf = vext_nf(desc);
|
||||
|
|
@ -626,22 +711,22 @@ void HELPER(NAME)(void *vd, target_ulong base, \
|
|||
ctzl(sizeof(ETYPE)), GETPC()); \
|
||||
}
|
||||
|
||||
GEN_VEXT_LD_WHOLE(vl1re8_v, int8_t, lde_b)
|
||||
GEN_VEXT_LD_WHOLE(vl1re16_v, int16_t, lde_h)
|
||||
GEN_VEXT_LD_WHOLE(vl1re32_v, int32_t, lde_w)
|
||||
GEN_VEXT_LD_WHOLE(vl1re64_v, int64_t, lde_d)
|
||||
GEN_VEXT_LD_WHOLE(vl2re8_v, int8_t, lde_b)
|
||||
GEN_VEXT_LD_WHOLE(vl2re16_v, int16_t, lde_h)
|
||||
GEN_VEXT_LD_WHOLE(vl2re32_v, int32_t, lde_w)
|
||||
GEN_VEXT_LD_WHOLE(vl2re64_v, int64_t, lde_d)
|
||||
GEN_VEXT_LD_WHOLE(vl4re8_v, int8_t, lde_b)
|
||||
GEN_VEXT_LD_WHOLE(vl4re16_v, int16_t, lde_h)
|
||||
GEN_VEXT_LD_WHOLE(vl4re32_v, int32_t, lde_w)
|
||||
GEN_VEXT_LD_WHOLE(vl4re64_v, int64_t, lde_d)
|
||||
GEN_VEXT_LD_WHOLE(vl8re8_v, int8_t, lde_b)
|
||||
GEN_VEXT_LD_WHOLE(vl8re16_v, int16_t, lde_h)
|
||||
GEN_VEXT_LD_WHOLE(vl8re32_v, int32_t, lde_w)
|
||||
GEN_VEXT_LD_WHOLE(vl8re64_v, int64_t, lde_d)
|
||||
GEN_VEXT_LD_WHOLE(vl1re8_v, int8_t, lde_b_tlb)
|
||||
GEN_VEXT_LD_WHOLE(vl1re16_v, int16_t, lde_h_tlb)
|
||||
GEN_VEXT_LD_WHOLE(vl1re32_v, int32_t, lde_w_tlb)
|
||||
GEN_VEXT_LD_WHOLE(vl1re64_v, int64_t, lde_d_tlb)
|
||||
GEN_VEXT_LD_WHOLE(vl2re8_v, int8_t, lde_b_tlb)
|
||||
GEN_VEXT_LD_WHOLE(vl2re16_v, int16_t, lde_h_tlb)
|
||||
GEN_VEXT_LD_WHOLE(vl2re32_v, int32_t, lde_w_tlb)
|
||||
GEN_VEXT_LD_WHOLE(vl2re64_v, int64_t, lde_d_tlb)
|
||||
GEN_VEXT_LD_WHOLE(vl4re8_v, int8_t, lde_b_tlb)
|
||||
GEN_VEXT_LD_WHOLE(vl4re16_v, int16_t, lde_h_tlb)
|
||||
GEN_VEXT_LD_WHOLE(vl4re32_v, int32_t, lde_w_tlb)
|
||||
GEN_VEXT_LD_WHOLE(vl4re64_v, int64_t, lde_d_tlb)
|
||||
GEN_VEXT_LD_WHOLE(vl8re8_v, int8_t, lde_b_tlb)
|
||||
GEN_VEXT_LD_WHOLE(vl8re16_v, int16_t, lde_h_tlb)
|
||||
GEN_VEXT_LD_WHOLE(vl8re32_v, int32_t, lde_w_tlb)
|
||||
GEN_VEXT_LD_WHOLE(vl8re64_v, int64_t, lde_d_tlb)
|
||||
|
||||
#define GEN_VEXT_ST_WHOLE(NAME, ETYPE, STORE_FN) \
|
||||
void HELPER(NAME)(void *vd, target_ulong base, \
|
||||
|
|
@ -651,10 +736,10 @@ void HELPER(NAME)(void *vd, target_ulong base, \
|
|||
ctzl(sizeof(ETYPE)), GETPC()); \
|
||||
}
|
||||
|
||||
GEN_VEXT_ST_WHOLE(vs1r_v, int8_t, ste_b)
|
||||
GEN_VEXT_ST_WHOLE(vs2r_v, int8_t, ste_b)
|
||||
GEN_VEXT_ST_WHOLE(vs4r_v, int8_t, ste_b)
|
||||
GEN_VEXT_ST_WHOLE(vs8r_v, int8_t, ste_b)
|
||||
GEN_VEXT_ST_WHOLE(vs1r_v, int8_t, ste_b_tlb)
|
||||
GEN_VEXT_ST_WHOLE(vs2r_v, int8_t, ste_b_tlb)
|
||||
GEN_VEXT_ST_WHOLE(vs4r_v, int8_t, ste_b_tlb)
|
||||
GEN_VEXT_ST_WHOLE(vs8r_v, int8_t, ste_b_tlb)
|
||||
|
||||
/*
|
||||
* Vector Integer Arithmetic Instructions
|
||||
|
|
|
|||
Loading…
Reference in New Issue