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aspeed: Implement write-1-{set, clear} for AST2500 strapping 

The AST2500 SoC family changes the runtime behaviour of the hardware
strapping register (SCU70) to write-1-set/write-1-clear, with
write-1-clear implemented on the "read-only" SoC revision register
(SCU7C). For the the AST2400, the hardware strapping is
runtime-configured with read-modify-write semantics.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-id: 20180709143524.17480-1-andrew@aj.id.au
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Andrew Jeffery 2018-07-16 17:18:41 +01:00 committed by Peter Maydell
parent 628fc75f3a
commit 333b9c8a68
2 changed files with 19 additions and 2 deletions
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19
hw/misc/aspeed_scu.c
View File

@ -247,11 +247,26 @@ static void aspeed_scu_write(void *opaque, hwaddr offset, uint64_t data,
s->regs[reg] = data;
aspeed_scu_set_apb_freq(s);
break;
case HW_STRAP1:
if (ASPEED_IS_AST2500(s->regs[SILICON_REV])) {
s->regs[HW_STRAP1] |= data;
return;
}
/* Jump to assignment below */
break;
case SILICON_REV:
if (ASPEED_IS_AST2500(s->regs[SILICON_REV])) {
s->regs[HW_STRAP1] &= ~data;
} else {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Write to read-only offset 0x%" HWADDR_PRIx "\n",
__func__, offset);
}
/* Avoid assignment below, we've handled everything */
return;
case FREQ_CNTR_EVAL:
case VGA_SCRATCH1 ... VGA_SCRATCH8:
case RNG_DATA:
case SILICON_REV:
case FREE_CNTR4:
case FREE_CNTR4_EXT:
qemu_log_mask(LOG_GUEST_ERROR,

2
include/hw/misc/aspeed_scu.h
View File

@ -41,6 +41,8 @@ typedef struct AspeedSCUState {
#define AST2500_A0_SILICON_REV 0x04000303U
#define AST2500_A1_SILICON_REV 0x04010303U
#define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) == 0x04)
extern bool is_supported_silicon_rev(uint32_t silicon_rev);
#define ASPEED_SCU_PROT_KEY 0x1688A8A8