mirror of https://github.com/xemu-project/xemu.git
target/riscv: Convert the RISC-V exceptions to an enum
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: f191dcf08bf413a822e743a7c7f824d68879a527.1617290165.git.alistair.francis@wdc.com
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@ -358,7 +358,7 @@ static void riscv_cpu_reset(DeviceState *dev)
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env->pc = env->resetvec;
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env->two_stage_lookup = false;
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#endif
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cs->exception_index = EXCP_NONE;
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cs->exception_index = RISCV_EXCP_NONE;
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env->load_res = -1;
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set_default_nan_mode(1, &env->fp_status);
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}
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@ -504,27 +504,29 @@
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#define DEFAULT_RSTVEC 0x1000
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/* Exception causes */
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#define EXCP_NONE -1 /* sentinel value */
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#define RISCV_EXCP_INST_ADDR_MIS 0x0
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#define RISCV_EXCP_INST_ACCESS_FAULT 0x1
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#define RISCV_EXCP_ILLEGAL_INST 0x2
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#define RISCV_EXCP_BREAKPOINT 0x3
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#define RISCV_EXCP_LOAD_ADDR_MIS 0x4
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#define RISCV_EXCP_LOAD_ACCESS_FAULT 0x5
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#define RISCV_EXCP_STORE_AMO_ADDR_MIS 0x6
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#define RISCV_EXCP_STORE_AMO_ACCESS_FAULT 0x7
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#define RISCV_EXCP_U_ECALL 0x8
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#define RISCV_EXCP_S_ECALL 0x9
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#define RISCV_EXCP_VS_ECALL 0xa
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#define RISCV_EXCP_M_ECALL 0xb
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#define RISCV_EXCP_INST_PAGE_FAULT 0xc /* since: priv-1.10.0 */
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#define RISCV_EXCP_LOAD_PAGE_FAULT 0xd /* since: priv-1.10.0 */
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#define RISCV_EXCP_STORE_PAGE_FAULT 0xf /* since: priv-1.10.0 */
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#define RISCV_EXCP_SEMIHOST 0x10
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#define RISCV_EXCP_INST_GUEST_PAGE_FAULT 0x14
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#define RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT 0x15
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#define RISCV_EXCP_VIRT_INSTRUCTION_FAULT 0x16
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#define RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT 0x17
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typedef enum RISCVException {
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RISCV_EXCP_NONE = -1, /* sentinel value */
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RISCV_EXCP_INST_ADDR_MIS = 0x0,
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RISCV_EXCP_INST_ACCESS_FAULT = 0x1,
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RISCV_EXCP_ILLEGAL_INST = 0x2,
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RISCV_EXCP_BREAKPOINT = 0x3,
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RISCV_EXCP_LOAD_ADDR_MIS = 0x4,
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RISCV_EXCP_LOAD_ACCESS_FAULT = 0x5,
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RISCV_EXCP_STORE_AMO_ADDR_MIS = 0x6,
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RISCV_EXCP_STORE_AMO_ACCESS_FAULT = 0x7,
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RISCV_EXCP_U_ECALL = 0x8,
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RISCV_EXCP_S_ECALL = 0x9,
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RISCV_EXCP_VS_ECALL = 0xa,
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RISCV_EXCP_M_ECALL = 0xb,
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RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */
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RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */
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RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */
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RISCV_EXCP_SEMIHOST = 0x10,
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RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,
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RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15,
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RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,
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RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17,
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} RISCVException;
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#define RISCV_EXCP_INT_FLAG 0x80000000
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#define RISCV_EXCP_INT_MASK 0x7fffffff
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@ -72,7 +72,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env)
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if (irqs) {
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return ctz64(irqs); /* since non-zero */
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} else {
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return EXCP_NONE; /* indicates no pending interrupt */
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return RISCV_EXCP_NONE; /* indicates no pending interrupt */
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}
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}
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#endif
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@ -1069,5 +1069,5 @@ void riscv_cpu_do_interrupt(CPUState *cs)
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env->two_stage_lookup = false;
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#endif
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cs->exception_index = EXCP_NONE; /* mark handled to qemu */
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cs->exception_index = RISCV_EXCP_NONE; /* mark handled to qemu */
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}
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