ShuriZma
/
xemu
mirror of https://github.com/xemu-project/xemu.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS 

PIIX_NUM_PIC_IRQS is assumed to be the same as ISA_NUM_IRQS, otherwise
inconsistencies can occur.

Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231007123843.127151-5-shentey@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Bernhard Beschow 2023-10-07 14:38:12 +02:00 committed by Michael S. Tsirkin
parent 8b6cf5128e
commit 32f29b26ff
2 changed files with 6 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
hw/isa/piix3.c
View File

@ -48,7 +48,7 @@ static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level)
uint64_t mask; uint64_t mask;
pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq]; pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
if (pic_irq >= PIIX_NUM_PIC_IRQS) { if (pic_irq >= ISA_NUM_IRQS) {
return; return;
} }
@ -62,7 +62,7 @@ static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
int pic_irq; int pic_irq;
pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq]; pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
if (pic_irq >= PIIX_NUM_PIC_IRQS) { if (pic_irq >= ISA_NUM_IRQS) {
return; return;
} }
@ -83,7 +83,7 @@ static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
int irq = piix3->dev.config[PIIX_PIRQCA + pin]; int irq = piix3->dev.config[PIIX_PIRQCA + pin];
PCIINTxRoute route; PCIINTxRoute route;
if (irq < PIIX_NUM_PIC_IRQS) { if (irq < ISA_NUM_IRQS) {
route.mode = PCI_INTX_ENABLED; route.mode = PCI_INTX_ENABLED;
route.irq = irq; route.irq = irq;
} else { } else {
@ -115,7 +115,7 @@ static void piix3_write_config(PCIDevice *dev,
pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev)); pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev));
piix3_update_irq_levels(piix3); piix3_update_irq_levels(piix3);
for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) { for (pic_irq = 0; pic_irq < ISA_NUM_IRQS; pic_irq++) {
piix3_set_irq_pic(piix3, pic_irq); piix3_set_irq_pic(piix3, pic_irq);
} }
} }

5
include/hw/southbridge/piix.h
View File

@ -27,7 +27,6 @@
*/ */
#define PIIX_RCR_IOPORT 0xcf9 #define PIIX_RCR_IOPORT 0xcf9
#define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */
#define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */ #define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */
struct PIIXState { struct PIIXState {
@ -39,10 +38,10 @@ struct PIIXState {
* So one PIC level is tracked by PIIX_NUM_PIRQS bits. * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
* *
* PIRQ is mapped to PIC pins, we track it by * PIRQ is mapped to PIC pins, we track it by
* PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with * PIIX_NUM_PIRQS * ISA_NUM_IRQS = 64 bits with
* pic_irq * PIIX_NUM_PIRQS + pirq * pic_irq * PIIX_NUM_PIRQS + pirq
*/ */
#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64 #if ISA_NUM_IRQS * PIIX_NUM_PIRQS > 64
#error "unable to encode pic state in 64bit in pic_levels." #error "unable to encode pic state in 64bit in pic_levels."
#endif #endif
uint64_t pic_levels; uint64_t pic_levels;