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x86, cpu queue, 2017-09-01 

CPU creation refactor plus x86 patches.
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Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-request' into staging

x86, cpu queue, 2017-09-01

CPU creation refactor plus x86 patches.

# gpg: Signature made Fri 01 Sep 2017 15:59:02 BST
# gpg:                using RSA key 0x2807936F984DC5A6
# gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>"
# Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF  D1AA 2807 936F 984D C5A6

* remotes/ehabkost/tags/x86-and-machine-pull-request: (29 commits)
  ppc: replace cpu_ppc_init() with cpu_generic_init()
  unicore32: replace uc32_cpu_init() with cpu_generic_init()
  openrisc: replace cpu_openrisc_init() with cpu_generic_init()
  moxie: replace cpu_moxie_init() with cpu_generic_init()
  lm32: replace cpu_lm32_init() with cpu_generic_init()
  x86: replace cpu_x86_init() with cpu_generic_init()
  cris: replace cpu_cris_init() with cpu_generic_init()
  arm: replace cpu_arm_init() with cpu_generic_init()
  sh4: replace cpu_sh4_init() with cpu_generic_init()
  tricore: replace cpu_tricore_init() with cpu_generic_init()
  xtensa: replace cpu_xtensa_init() with cpu_generic_init()
  tilegx: replace cpu_tilegx_init() with cpu_generic_init()
  nios2: replace cpu_nios2_init() with cpu_generic_init()
  microblaze: replace cpu_mb_init() with cpu_generic_init()
  m68k: replace cpu_m68k_init() with cpu_generic_init()
  hppa: replace cpu_hppa_init() with cpu_generic_init()
  alpha: replace cpu_alpha_init() with cpu_generic_init()
  s390x: replace cpu_s390x_init() with cpu_generic_init()
  sparc: replace cpu_sparc_init() with cpu_generic_init()
  sparc: make cpu feature parsing property based
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2017-09-01 17:28:54 +01:00
parent 223cd0e13f 84efa64c60
commit 32f0f68bb7
88 changed files with 422 additions and 450 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
backends/cryptodev.c
View File

@ -215,7 +215,7 @@ bool cryptodev_backend_is_ready(CryptoDevBackend *backend)
}
static bool
cryptodev_backend_can_be_deleted(UserCreatable *uc, Error **errp)
cryptodev_backend_can_be_deleted(UserCreatable *uc)
{
return !cryptodev_backend_is_used(CRYPTODEV_BACKEND(uc));
}

2
backends/hostmem.c
View File

@ -342,7 +342,7 @@ out:
}
static bool
host_memory_backend_can_be_deleted(UserCreatable *uc, Error **errp)
host_memory_backend_can_be_deleted(UserCreatable *uc)
{
if (host_memory_backend_is_mapped(MEMORY_BACKEND(uc))) {
return false;

7
hmp-commands-info.hx
View File

@ -115,9 +115,10 @@ ETEXI
#if defined(TARGET_I386)
{
.name = "lapic",
.args_type = "",
.params = "",
.help = "show local apic state",
.args_type = "apic-id:i?",
.params = "[apic-id]",
.help = "show local apic state (apic-id: local apic to read, default is which of current CPU)",
.cmd = hmp_info_local_apic,
},
#endif

8
hw/alpha/dp264.c
View File

@ -51,7 +51,7 @@ static int clipper_pci_map_irq(PCIDevice *d, int irq_num)
static void clipper_init(MachineState *machine)
{
ram_addr_t ram_size = machine->ram_size;
const char *cpu_model = machine->cpu_model;
const char *cpu_model = machine->cpu_model ? machine->cpu_model : "ev67";
const char *kernel_filename = machine->kernel_filename;
const char *kernel_cmdline = machine->kernel_cmdline;
const char *initrd_filename = machine->initrd_filename;
@ -67,7 +67,11 @@ static void clipper_init(MachineState *machine)
/* Create up to 4 cpus. */
memset(cpus, 0, sizeof(cpus));
for (i = 0; i < smp_cpus; ++i) {
cpus[i] = cpu_alpha_init(cpu_model ? cpu_model : "ev67");
cpus[i] = ALPHA_CPU(cpu_generic_init(TYPE_ALPHA_CPU, cpu_model));
if (!cpus[i]) {
error_report("Unable to find CPU definition");
exit(1);
}
}
cpus[0]->env.trap_arg0 = ram_size;

2
hw/arm/musicpal.c
View File

@ -1593,7 +1593,7 @@ static void musicpal_init(MachineState *machine)
if (!cpu_model) {
cpu_model = "arm926";
}
cpu = cpu_arm_init(cpu_model);
cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model));
if (!cpu) {
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);

2
hw/arm/omap1.c
View File

@ -3863,7 +3863,7 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
/* Core */
s->mpu_model = omap310;
s->cpu = cpu_arm_init(core);
s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, core));
if (s->cpu == NULL) {
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);

2
hw/arm/omap2.c
View File

@ -2261,7 +2261,7 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,
/* Core */
s->mpu_model = omap2420;
s->cpu = cpu_arm_init(core ?: "arm1136-r2");
s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, core ?: "arm1136-r2"));
if (s->cpu == NULL) {
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);

4
hw/arm/pxa2xx.c
View File

@ -2066,7 +2066,7 @@ PXA2xxState *pxa270_init(MemoryRegion *address_space,
if (!revision)
revision = "pxa270";
s->cpu = cpu_arm_init(revision);
s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, revision));
if (s->cpu == NULL) {
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
@ -2196,7 +2196,7 @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)
s = g_new0(PXA2xxState, 1);
s->cpu = cpu_arm_init("pxa255");
s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, "pxa255"));
if (s->cpu == NULL) {
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);

2
hw/arm/strongarm.c
View File

@ -1597,7 +1597,7 @@ StrongARMState *sa1110_init(MemoryRegion *sysmem,
exit(1);
}
s->cpu = cpu_arm_init(rev);
s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, rev));
if (!s->cpu) {
error_report("Unable to find CPU definition");

2
hw/cris/axis_dev88.c
View File

@ -271,7 +271,7 @@ void axisdev88_init(MachineState *machine)
if (cpu_model == NULL) {
cpu_model = "crisv32";
}
cpu = cpu_cris_init(cpu_model);
cpu = CRIS_CPU(cpu_generic_init(TYPE_CRIS_CPU, cpu_model));
env = &cpu->env;
/* allocate RAM */

4
hw/lm32/lm32_boards.c
View File

@ -104,7 +104,7 @@ static void lm32_evr_init(MachineState *machine)
if (cpu_model == NULL) {
cpu_model = "lm32-full";
}
cpu = cpu_lm32_init(cpu_model);
cpu = LM32_CPU(cpu_generic_init(TYPE_LM32_CPU, cpu_model));
if (cpu == NULL) {
fprintf(stderr, "qemu: unable to find CPU '%s'\n", cpu_model);
exit(1);
@ -205,7 +205,7 @@ static void lm32_uclinux_init(MachineState *machine)
if (cpu_model == NULL) {
cpu_model = "lm32-full";
}
cpu = cpu_lm32_init(cpu_model);
cpu = LM32_CPU(cpu_generic_init(TYPE_LM32_CPU, cpu_model));
if (cpu == NULL) {
fprintf(stderr, "qemu: unable to find CPU '%s'\n", cpu_model);
exit(1);

2
hw/lm32/milkymist.c
View File

@ -111,7 +111,7 @@ milkymist_init(MachineState *machine)
if (cpu_model == NULL) {
cpu_model = "lm32-full";
}
cpu = cpu_lm32_init(cpu_model);
cpu = LM32_CPU(cpu_generic_init(TYPE_LM32_CPU, cpu_model));
if (cpu == NULL) {
fprintf(stderr, "qemu: unable to find CPU '%s'\n", cpu_model);
exit(1);

2
hw/m68k/an5206.c
View File

@ -42,7 +42,7 @@ static void an5206_init(MachineState *machine)
if (!cpu_model) {
cpu_model = "m5206";
}
cpu = cpu_m68k_init(cpu_model);
cpu = M68K_CPU(cpu_generic_init(TYPE_M68K_CPU, cpu_model));
if (!cpu) {
error_report("Unable to find m68k CPU definition");
exit(1);

2
hw/m68k/mcf5208.c
View File

@ -232,7 +232,7 @@ static void mcf5208evb_init(MachineState *machine)
if (!cpu_model) {
cpu_model = "m5208";
}
cpu = cpu_m68k_init(cpu_model);
cpu = M68K_CPU(cpu_generic_init(TYPE_M68K_CPU, cpu_model));
if (!cpu) {
fprintf(stderr, "Unable to find m68k CPU definition\n");
exit(1);

2
hw/moxie/moxiesim.c
View File

@ -118,7 +118,7 @@ static void moxiesim_init(MachineState *machine)
if (cpu_model == NULL) {
cpu_model = "MoxieLite-moxie-cpu";
}
cpu = cpu_moxie_init(cpu_model);
cpu = MOXIE_CPU(cpu_generic_init(TYPE_MOXIE_CPU, cpu_model));
if (!cpu) {
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);

2
hw/nios2/10m50_devboard.c
View File

@ -75,7 +75,7 @@ static void nios2_10m50_ghrd_init(MachineState *machine)
phys_ram_alias);
/* Create CPU -- FIXME */
cpu = cpu_nios2_init("nios2");
cpu = NIOS2_CPU(cpu_generic_init(TYPE_NIOS2_CPU, "nios2"));
/* Register: CPU interrupt controller (PIC) */
cpu_irq = nios2_cpu_pic_init(cpu);

2
hw/openrisc/openrisc_sim.c
View File

@ -109,7 +109,7 @@ static void openrisc_sim_init(MachineState *machine)
}
for (n = 0; n < smp_cpus; n++) {
cpu = cpu_openrisc_init(cpu_model);
cpu = OPENRISC_CPU(cpu_generic_init(TYPE_OPENRISC_CPU, cpu_model));
if (cpu == NULL) {
fprintf(stderr, "Unable to find CPU definition!\n");
exit(1);

3
hw/ppc/e500.c
View File

@ -819,7 +819,8 @@ void ppce500_init(MachineState *machine, PPCE500Params *params)
CPUState *cs;
qemu_irq *input;
cpu = cpu_ppc_init(machine->cpu_model);
cpu = POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU,
machine->cpu_model));
if (cpu == NULL) {
fprintf(stderr, "Unable to initialize CPU!\n");
exit(1);

3
hw/ppc/mac_newworld.c
View File

@ -187,7 +187,8 @@ static void ppc_core99_init(MachineState *machine)
#endif
}
for (i = 0; i < smp_cpus; i++) {
cpu = cpu_ppc_init(machine->cpu_model);
cpu = POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU,
machine->cpu_model));
if (cpu == NULL) {
fprintf(stderr, "Unable to find PowerPC CPU definition\n");
exit(1);

3
hw/ppc/mac_oldworld.c
View File

@ -116,7 +116,8 @@ static void ppc_heathrow_init(MachineState *machine)
if (machine->cpu_model == NULL)
machine->cpu_model = "G3";
for (i = 0; i < smp_cpus; i++) {
cpu = cpu_ppc_init(machine->cpu_model);
cpu = POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU,
machine->cpu_model));
if (cpu == NULL) {
fprintf(stderr, "Unable to find PowerPC CPU definition\n");
exit(1);

2
hw/ppc/ppc440_bamboo.c
View File

@ -186,7 +186,7 @@ static void bamboo_init(MachineState *machine)
if (machine->cpu_model == NULL) {
machine->cpu_model = "440EP";
}
cpu = cpu_ppc_init(machine->cpu_model);
cpu = POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU, machine->cpu_model));
if (cpu == NULL) {
fprintf(stderr, "Unable to initialize CPU!\n");
exit(1);

2
hw/ppc/ppc4xx_devs.c
View File

@ -56,7 +56,7 @@ PowerPCCPU *ppc4xx_init(const char *cpu_model,
CPUPPCState *env;
/* init CPUs */
cpu = cpu_ppc_init(cpu_model);
cpu = POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU, cpu_model));
if (cpu == NULL) {
fprintf(stderr, "Unable to find PowerPC %s CPU definition\n",
cpu_model);

5
hw/ppc/prep.c
View File

@ -520,7 +520,8 @@ static void ppc_prep_init(MachineState *machine)
if (machine->cpu_model == NULL)
machine->cpu_model = "602";
for (i = 0; i < smp_cpus; i++) {
cpu = cpu_ppc_init(machine->cpu_model);
cpu = POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU,
machine->cpu_model));
if (cpu == NULL) {
fprintf(stderr, "Unable to find PowerPC CPU definition\n");
exit(1);
@ -724,7 +725,7 @@ static void ibm_40p_init(MachineState *machine)
if (!machine->cpu_model) {
machine->cpu_model = "604";
}
cpu = cpu_ppc_init(machine->cpu_model);
cpu = POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU, machine->cpu_model));
if (!cpu) {
error_report("could not initialize CPU '%s'",
machine->cpu_model);

2
hw/ppc/virtex_ml507.c
View File

@ -96,7 +96,7 @@ static PowerPCCPU *ppc440_init_xilinx(ram_addr_t *ram_size,
CPUPPCState *env;
qemu_irq *irqs;
cpu = cpu_ppc_init(cpu_model);
cpu = POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU, cpu_model));
if (cpu == NULL) {
fprintf(stderr, "Unable to initialize CPU!\n");
exit(1);

2
hw/sh4/r2d.c
View File

@ -246,7 +246,7 @@ static void r2d_init(MachineState *machine)
cpu_model = "SH7751R";
}
cpu = cpu_sh4_init(cpu_model);
cpu = SUPERH_CPU(cpu_generic_init(TYPE_SUPERH_CPU, cpu_model));
if (cpu == NULL) {
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);

2
hw/sh4/shix.c
View File

@ -56,7 +56,7 @@ static void shix_init(MachineState *machine)
if (!cpu_model)
cpu_model = "any";
cpu = cpu_sh4_init(cpu_model);
cpu = SUPERH_CPU(cpu_generic_init(TYPE_SUPERH_CPU, cpu_model));
if (cpu == NULL) {
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);

2
hw/sparc/leon3.c
View File

@ -126,7 +126,7 @@ static void leon3_generic_hw_init(MachineState *machine)
cpu_model = "LEON3";
}
cpu = cpu_sparc_init(cpu_model);
cpu = SPARC_CPU(cpu_generic_init(TYPE_SPARC_CPU, cpu_model));
if (cpu == NULL) {
fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
exit(1);

2
hw/sparc/sun4m.c
View File

@ -797,7 +797,7 @@ static void cpu_devinit(const char *cpu_model, unsigned int id,
SPARCCPU *cpu;
CPUSPARCState *env;
cpu = cpu_sparc_init(cpu_model);
cpu = SPARC_CPU(cpu_generic_init(TYPE_SPARC_CPU, cpu_model));
if (cpu == NULL) {
fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
exit(1);

2
hw/sparc64/sparc64.c
View File

@ -353,7 +353,7 @@ SPARCCPU *sparc64_cpu_devinit(const char *cpu_model,
if (cpu_model == NULL) {
cpu_model = default_cpu_model;
}
cpu = cpu_sparc_init(cpu_model);
cpu = SPARC_CPU(cpu_generic_init(TYPE_SPARC_CPU, cpu_model));
if (cpu == NULL) {
fprintf(stderr, "Unable to find Sparc CPU definition\n");
exit(1);

2
hw/tricore/tricore_testboard.c
View File

@ -74,7 +74,7 @@ static void tricore_testboard_init(MachineState *machine, int board_id)
if (!machine->cpu_model) {
machine->cpu_model = "tc1796";
}
cpu = cpu_tricore_init(machine->cpu_model);
cpu = TRICORE_CPU(cpu_generic_init(TYPE_TRICORE_CPU, machine->cpu_model));
if (!cpu) {
error_report("Unable to find CPU definition");
exit(1);

2
hw/unicore32/puv3.c
View File

@ -127,7 +127,7 @@ static void puv3_init(MachineState *machine)
cpu_model = "UniCore-II";
}
cpu = uc32_cpu_init(cpu_model);
cpu = UNICORE32_CPU(cpu_generic_init(TYPE_UNICORE32_CPU, cpu_model));
if (!cpu) {
error_report("Unable to find CPU definition");
exit(1);

2
hw/xtensa/sim.c
View File

@ -84,7 +84,7 @@ static void xtensa_sim_init(MachineState *machine)
}
for (n = 0; n < smp_cpus; n++) {
cpu = cpu_xtensa_init(cpu_model);
cpu = XTENSA_CPU(cpu_generic_init(TYPE_XTENSA_CPU, cpu_model));
if (cpu == NULL) {
error_report("unable to find CPU definition '%s'",
cpu_model);

2
hw/xtensa/xtfpga.c
View File

@ -232,7 +232,7 @@ static void lx_init(const LxBoardDesc *board, MachineState *machine)
}
for (n = 0; n < smp_cpus; n++) {
cpu = cpu_xtensa_init(cpu_model);
cpu = XTENSA_CPU(cpu_generic_init(TYPE_XTENSA_CPU, cpu_model));
if (cpu == NULL) {
error_report("unable to find CPU definition '%s'",
cpu_model);

10
include/qom/cpu.h
View File

@ -754,6 +754,16 @@ CPUState *qemu_get_cpu(int index);
*/
bool cpu_exists(int64_t id);
/**
* cpu_by_arch_id:
* @id: Guest-exposed CPU ID of the CPU to obtain.
*
* Get a CPU with matching @id.
*
* Returns: The CPU or %NULL if there is no matching CPU.
*/
CPUState *cpu_by_arch_id(int64_t id);
/**
* cpu_throttle_set:
* @new_throttle_pct: Percent of sleep time. Valid range is 1 to 99.

5
include/qom/object_interfaces.h
View File

@ -51,7 +51,7 @@ typedef struct UserCreatableClass {
/* <public> */
void (*complete)(UserCreatable *uc, Error **errp);
bool (*can_be_deleted)(UserCreatable *uc, Error **errp);
bool (*can_be_deleted)(UserCreatable *uc);
} UserCreatableClass;
/**
@ -68,12 +68,11 @@ void user_creatable_complete(Object *obj, Error **errp);
/**
* user_creatable_can_be_deleted:
* @uc: the object whose can_be_deleted() method is called if implemented
* @errp: if an error occurs, a pointer to an area to store the error
*
* Wrapper to call can_be_deleted() method if one of types it's inherited
* from implements USER_CREATABLE interface.
*/
bool user_creatable_can_be_deleted(UserCreatable *uc, Error **errp);
bool user_creatable_can_be_deleted(UserCreatable *uc);
/**
* user_creatable_add_type:

2
linux-user/sparc/target_syscall.h
View File

@ -31,7 +31,7 @@ struct target_pt_regs {
static inline abi_ulong target_shmlba(CPUSPARCState *env)
{
if (!(env->def->features & CPU_FEATURE_FLUSH)) {
if (!(env->def.features & CPU_FEATURE_FLUSH)) {
return 64 * 1024;
} else {
return 256 * 1024;

25
qom/cpu.c
View File

@ -34,7 +34,7 @@
CPUInterruptHandler cpu_interrupt_handler;
bool cpu_exists(int64_t id)
CPUState *cpu_by_arch_id(int64_t id)
{
CPUState *cpu;
@ -42,36 +42,39 @@ bool cpu_exists(int64_t id)
CPUClass *cc = CPU_GET_CLASS(cpu);
if (cc->get_arch_id(cpu) == id) {
return true;
return cpu;
}
}
return false;
return NULL;
}
bool cpu_exists(int64_t id)
{
return !!cpu_by_arch_id(id);
}
CPUState *cpu_generic_init(const char *typename, const char *cpu_model)
{
char *str, *name, *featurestr;
CPUState *cpu = NULL;
ObjectClass *oc;
CPUClass *cc;
Error *err = NULL;
gchar **model_pieces;
str = g_strdup(cpu_model);
name = strtok(str, ",");
model_pieces = g_strsplit(cpu_model, ",", 2);
oc = cpu_class_by_name(typename, name);
oc = cpu_class_by_name(typename, model_pieces[0]);
if (oc == NULL) {
g_free(str);
g_strfreev(model_pieces);
return NULL;
}
cc = CPU_CLASS(oc);
featurestr = strtok(NULL, ",");
/* TODO: all callers of cpu_generic_init() need to be converted to
* call parse_features() only once, before calling cpu_generic_init().
*/
cc->parse_features(object_class_get_name(oc), featurestr, &err);
g_free(str);
cc->parse_features(object_class_get_name(oc), model_pieces[1], &err);
g_strfreev(model_pieces);
if (err != NULL) {
goto out;
}

6
qom/object_interfaces.c
View File

@ -23,13 +23,13 @@ void user_creatable_complete(Object *obj, Error **errp)
}
}
bool user_creatable_can_be_deleted(UserCreatable *uc, Error **errp)
bool user_creatable_can_be_deleted(UserCreatable *uc)
{
UserCreatableClass *ucc = USER_CREATABLE_GET_CLASS(uc);
if (ucc->can_be_deleted) {
return ucc->can_be_deleted(uc, errp);
return ucc->can_be_deleted(uc);
} else {
return true;
}
@ -178,7 +178,7 @@ void user_creatable_del(const char *id, Error **errp)
return;
}
if (!user_creatable_can_be_deleted(USER_CREATABLE(obj), errp)) {
if (!user_creatable_can_be_deleted(USER_CREATABLE(obj))) {
error_setg(errp, "object '%s' is in use, can not be deleted", id);
return;
}

20
target/alpha/cpu.c
View File

@ -155,24 +155,14 @@ static ObjectClass *alpha_cpu_class_by_name(const char *cpu_model)
if (oc != NULL && object_class_is_abstract(oc)) {
oc = NULL;
}
return oc;
}
AlphaCPU *cpu_alpha_init(const char *cpu_model)
{
AlphaCPU *cpu;
ObjectClass *cpu_class;
cpu_class = alpha_cpu_class_by_name(cpu_model);
if (cpu_class == NULL) {
/* Default to ev67; no reason not to emulate insns by default. */
cpu_class = object_class_by_name(TYPE("ev67"));
/* TODO: remove match everything nonsense */
/* Default to ev67; no reason not to emulate insns by default. */
if (!oc) {
oc = object_class_by_name(TYPE("ev67"));
}
cpu = ALPHA_CPU(object_new(object_class_get_name(cpu_class)));
object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
return cpu;
return oc;
}
static void ev4_cpu_initfn(Object *obj)

4
target/alpha/cpu.h
View File

@ -468,9 +468,7 @@ enum {
void alpha_translate_init(void);
AlphaCPU *cpu_alpha_init(const char *cpu_model);
#define cpu_init(cpu_model) CPU(cpu_alpha_init(cpu_model))
#define cpu_init(cpu_model) cpu_generic_init(TYPE_ALPHA_CPU, cpu_model)
void alpha_cpu_list(FILE *f, fprintf_function cpu_fprintf);
/* you can call this signal handler from your SIGBUS and SIGSEGV

3
target/arm/cpu.h
View File

@ -748,7 +748,6 @@ int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
#endif
ARMCPU *cpu_arm_init(const char *cpu_model);
target_ulong do_arm_semihosting(CPUARMState *env);
void aarch64_sync_32_to_64(CPUARMState *env);
void aarch64_sync_64_to_32(CPUARMState *env);
@ -2001,7 +2000,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
return unmasked || pstate_unmasked;
}
#define cpu_init(cpu_model) CPU(cpu_arm_init(cpu_model))
#define cpu_init(cpu_model) cpu_generic_init(TYPE_ARM_CPU, cpu_model)
#define cpu_signal_handler cpu_arm_signal_handler
#define cpu_list arm_cpu_list

5
target/arm/helper.c
View File

@ -5233,11 +5233,6 @@ void register_cp_regs_for_features(ARMCPU *cpu)
}
}
ARMCPU *cpu_arm_init(const char *cpu_model)
{
return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model));
}
void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
{
CPUState *cs = CPU(cpu);

5
target/cris/cpu.c
View File

@ -89,11 +89,6 @@ static ObjectClass *cris_cpu_class_by_name(const char *cpu_model)
return oc;
}
CRISCPU *cpu_cris_init(const char *cpu_model)
{
return CRIS_CPU(cpu_generic_init(TYPE_CRIS_CPU, cpu_model));
}
/* Sort alphabetically by VR. */
static gint cris_cpu_list_compare(gconstpointer a, gconstpointer b)
{

3
target/cris/cpu.h
View File

@ -216,7 +216,6 @@ int crisv10_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
int cris_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
int cris_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
CRISCPU *cpu_cris_init(const char *cpu_model);
/* you can call this signal handler from your SIGBUS and SIGSEGV
signal handlers to inform the virtual CPU of exceptions. non zero
is returned if the signal was handled by the virtual CPU. */
@ -268,7 +267,7 @@ enum {
#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
#define cpu_init(cpu_model) CPU(cpu_cris_init(cpu_model))
#define cpu_init(cpu_model) cpu_generic_init(TYPE_CRIS_CPU, cpu_model)
#define cpu_signal_handler cpu_cris_signal_handler

11
target/hppa/cpu.c
View File

@ -112,15 +112,9 @@ static void hppa_cpu_initfn(Object *obj)
hppa_translate_init();
}
HPPACPU *cpu_hppa_init(const char *cpu_model)
static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model)
{
HPPACPU *cpu;
cpu = HPPA_CPU(object_new(TYPE_HPPA_CPU));
object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
return cpu;
return object_class_by_name(TYPE_HPPA_CPU);
}
static void hppa_cpu_class_init(ObjectClass *oc, void *data)
@ -132,6 +126,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
acc->parent_realize = dc->realize;
dc->realize = hppa_cpu_realizefn;
cc->class_by_name = hppa_cpu_class_by_name;
cc->do_interrupt = hppa_cpu_do_interrupt;
cc->cpu_exec_interrupt = hppa_cpu_exec_interrupt;
cc->dump_state = hppa_cpu_dump_state;

4
target/hppa/cpu.h
View File

@ -112,9 +112,7 @@ static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch)
void hppa_translate_init(void);
HPPACPU *cpu_hppa_init(const char *cpu_model);
#define cpu_init(cpu_model) CPU(cpu_hppa_init(cpu_model))
#define cpu_init(cpu_model) cpu_generic_init(TYPE_HPPA_CPU, cpu_model)
void hppa_cpu_list(FILE *f, fprintf_function cpu_fprintf);

49
target/i386/cpu.c
View File

@ -1522,6 +1522,50 @@ static X86CPUDefinition builtin_x86_defs[] = {
.xlevel = 0x8000001A,
.model_id = "AMD Opteron 63xx class CPU",
},
{
.name = "EPYC",
.level = 0xd,
.vendor = CPUID_VENDOR_AMD,
.family = 23,
.model = 1,
.stepping = 2,
.features[FEAT_1_EDX] =
CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
CPUID_VME | CPUID_FP87,
.features[FEAT_1_ECX] =
CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
.features[FEAT_8000_0001_EDX] =
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
CPUID_EXT2_SYSCALL,
.features[FEAT_8000_0001_ECX] =
CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
.features[FEAT_7_0_EBX] =
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
CPUID_7_0_EBX_SHA_NI,
/* Missing: XSAVES (not supported by some Linux versions,
* including v4.1 to v4.12).
* KVM doesn't yet expose any XSAVES state save component.
*/
.features[FEAT_XSAVE] =
CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
CPUID_XSAVE_XGETBV1,
.features[FEAT_6_EAX] =
CPUID_6_EAX_ARAT,
.xlevel = 0x8000000A,
.model_id = "AMD EPYC Processor",
},
};
typedef struct PropValue {
@ -2642,11 +2686,6 @@ static gchar *x86_gdb_arch_name(CPUState *cs)
#endif
}
X86CPU *cpu_x86_init(const char *cpu_model)
{
return X86_CPU(cpu_generic_init(TYPE_X86_CPU, cpu_model));
}
static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
{
X86CPUDefinition *cpudef = data;

3
target/i386/cpu.h
View File

@ -1327,7 +1327,6 @@ int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
void x86_cpu_exec_enter(CPUState *cpu);
void x86_cpu_exec_exit(CPUState *cpu);
X86CPU *cpu_x86_init(const char *cpu_model);
void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf);
int cpu_x86_support_mca_broadcast(CPUX86State *env);
@ -1507,7 +1506,7 @@ uint64_t cpu_get_tsc(CPUX86State *env);
#define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS)
#define cpu_init(cpu_model) CPU(cpu_x86_init(cpu_model))
#define cpu_init(cpu_model) cpu_generic_init(TYPE_X86_CPU, cpu_model)
#define cpu_signal_handler cpu_x86_signal_handler
#define cpu_list x86_cpu_list

10
target/i386/monitor.c
View File

@ -632,7 +632,15 @@ const MonitorDef *target_monitor_defs(void)
void hmp_info_local_apic(Monitor *mon, const QDict *qdict)
{
CPUState *cs = mon_get_cpu();
CPUState *cs;
if (qdict_haskey(qdict, "apic-id")) {
int id = qdict_get_try_int(qdict, "apic-id", 0);
cs = cpu_by_arch_id(id);
} else {
cs = mon_get_cpu();
}
if (!cs) {
monitor_printf(mon, "No CPU available\n");

3
target/lm32/cpu.h
View File

@ -238,7 +238,6 @@ static inline lm32_wp_t lm32_wp_type(uint32_t dc, int idx)
return (dc >> (idx+1)*2) & 0x3;
}
LM32CPU *cpu_lm32_init(const char *cpu_model);
/* you can call this signal handler from your SIGBUS and SIGSEGV
signal handlers to inform the virtual CPU of exceptions. non zero
is returned if the signal was handled by the virtual CPU. */
@ -256,7 +255,7 @@ void lm32_watchpoint_insert(CPULM32State *env, int index, target_ulong address,
void lm32_watchpoint_remove(CPULM32State *env, int index);
bool lm32_cpu_do_semihosting(CPUState *cs);
#define cpu_init(cpu_model) CPU(cpu_lm32_init(cpu_model))
#define cpu_init(cpu_model) cpu_generic_init(TYPE_LM32_CPU, cpu_model)
#define cpu_list lm32_cpu_list
#define cpu_signal_handler cpu_lm32_signal_handler

5
target/lm32/helper.c
View File

@ -219,11 +219,6 @@ bool lm32_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
return false;
}
LM32CPU *cpu_lm32_init(const char *cpu_model)
{
return LM32_CPU(cpu_generic_init(TYPE_LM32_CPU, cpu_model));
}
/* Some soc ignores the MSB on the address bus. Thus creating a shadow memory
* area. As a general rule, 0x00000000-0x7fffffff is cached, whereas
* 0x80000000-0xffffffff is not cached and used to access IO devices. */

2
target/m68k/cpu.c
View File

@ -230,6 +230,8 @@ static void m68k_cpu_realizefn(DeviceState *dev, Error **errp)
M68kCPUClass *mcc = M68K_CPU_GET_CLASS(dev);
Error *local_err = NULL;
register_m68k_insns(&cpu->env);
cpu_exec_realizefn(cs, &local_err);
if (local_err != NULL) {
error_propagate(errp, local_err);

3
target/m68k/cpu.h
View File

@ -163,7 +163,6 @@ int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
void m68k_tcg_init(void);
void m68k_cpu_init_gdb(M68kCPU *cpu);
M68kCPU *cpu_m68k_init(const char *cpu_model);
/* you can call this signal handler from your SIGBUS and SIGSEGV
signal handlers to inform the virtual CPU of exceptions. non zero
is returned if the signal was handled by the virtual CPU. */
@ -322,7 +321,7 @@ void register_m68k_insns (CPUM68KState *env);
#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
#define cpu_init(cpu_model) CPU(cpu_m68k_init(cpu_model))
#define cpu_init(cpu_model) cpu_generic_init(TYPE_M68K_CPU, cpu_model)
#define cpu_signal_handler cpu_m68k_signal_handler
#define cpu_list m68k_cpu_list

20
target/m68k/helper.c
View File

@ -156,26 +156,6 @@ static int m68k_fpu_gdb_set_reg(CPUM68KState *env, uint8_t *mem_buf, int n)
return 0;
}
M68kCPU *cpu_m68k_init(const char *cpu_model)
{
M68kCPU *cpu;
CPUM68KState *env;
ObjectClass *oc;
oc = cpu_class_by_name(TYPE_M68K_CPU, cpu_model);
if (oc == NULL) {
return NULL;
}
cpu = M68K_CPU(object_new(object_class_get_name(oc)));
env = &cpu->env;
register_m68k_insns(env);
object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
return cpu;
}
void m68k_cpu_init_gdb(M68kCPU *cpu)
{
CPUState *cs = CPU(cpu);

6
target/microblaze/cpu.c
View File

@ -253,6 +253,11 @@ static Property mb_properties[] = {
DEFINE_PROP_END_OF_LIST(),
};
static ObjectClass *mb_cpu_class_by_name(const char *cpu_model)
{
return object_class_by_name(TYPE_MICROBLAZE_CPU);
}
static void mb_cpu_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
@ -265,6 +270,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
mcc->parent_reset = cc->reset;
cc->reset = mb_cpu_reset;
cc->class_by_name = mb_cpu_class_by_name;
cc->has_work = mb_cpu_has_work;
cc->do_interrupt = mb_cpu_do_interrupt;
cc->cpu_exec_interrupt = mb_cpu_exec_interrupt;

3
target/microblaze/cpu.h
View File

@ -331,7 +331,6 @@ int mb_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
int mb_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
void mb_tcg_init(void);
MicroBlazeCPU *cpu_mb_init(const char *cpu_model);
/* you can call this signal handler from your SIGBUS and SIGSEGV
signal handlers to inform the virtual CPU of exceptions. non zero
is returned if the signal was handled by the virtual CPU. */
@ -344,7 +343,7 @@ int cpu_mb_signal_handler(int host_signum, void *pinfo,
#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
#define cpu_init(cpu_model) CPU(cpu_mb_init(cpu_model))
#define cpu_init(cpu_model) cpu_generic_init(TYPE_MICROBLAZE_CPU, cpu_model)
#define cpu_signal_handler cpu_mb_signal_handler

11
target/microblaze/translate.c
View File

@ -1845,17 +1845,6 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
cpu_fprintf(f, "\n\n");
}
MicroBlazeCPU *cpu_mb_init(const char *cpu_model)
{
MicroBlazeCPU *cpu;
cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU));
object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
return cpu;
}
void mb_tcg_init(void)
{
int i;

5
target/moxie/cpu.c
View File

@ -150,11 +150,6 @@ static const MoxieCPUInfo moxie_cpus[] = {
{ .name = "any", .initfn = moxie_any_initfn },
};
MoxieCPU *cpu_moxie_init(const char *cpu_model)
{
return MOXIE_CPU(cpu_generic_init(TYPE_MOXIE_CPU, cpu_model));
}
static void cpu_register(const MoxieCPUInfo *info)
{
TypeInfo type_info = {

3
target/moxie/cpu.h
View File

@ -112,7 +112,6 @@ static inline MoxieCPU *moxie_env_get_cpu(CPUMoxieState *env)
#define ENV_OFFSET offsetof(MoxieCPU, env)
MoxieCPU *cpu_moxie_init(const char *cpu_model);
void moxie_cpu_do_interrupt(CPUState *cs);
void moxie_cpu_dump_state(CPUState *cpu, FILE *f,
fprintf_function cpu_fprintf, int flags);
@ -121,7 +120,7 @@ void moxie_translate_init(void);
int cpu_moxie_signal_handler(int host_signum, void *pinfo,
void *puc);
#define cpu_init(cpu_model) CPU(cpu_moxie_init(cpu_model))
#define cpu_init(cpu_model) cpu_generic_init(TYPE_MOXIE_CPU, cpu_model)
#define cpu_signal_handler cpu_moxie_signal_handler

9
target/nios2/cpu.c
View File

@ -83,13 +83,9 @@ static void nios2_cpu_initfn(Object *obj)
}
}
Nios2CPU *cpu_nios2_init(const char *cpu_model)
static ObjectClass *nios2_cpu_class_by_name(const char *cpu_model)
{
Nios2CPU *cpu = NIOS2_CPU(object_new(TYPE_NIOS2_CPU));
object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
return cpu;
return object_class_by_name(TYPE_NIOS2_CPU);
}
static void nios2_cpu_realizefn(DeviceState *dev, Error **errp)
@ -203,6 +199,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data)
ncc->parent_reset = cc->reset;
cc->reset = nios2_cpu_reset;
cc->class_by_name = nios2_cpu_class_by_name;
cc->has_work = nios2_cpu_has_work;
cc->do_interrupt = nios2_cpu_do_interrupt;
cc->cpu_exec_interrupt = nios2_cpu_exec_interrupt;

3
target/nios2/cpu.h
View File

@ -212,7 +212,6 @@ static inline Nios2CPU *nios2_env_get_cpu(CPUNios2State *env)
#define ENV_OFFSET offsetof(Nios2CPU, env)
void nios2_tcg_init(void);
Nios2CPU *cpu_nios2_init(const char *cpu_model);
void nios2_cpu_do_interrupt(CPUState *cs);
int cpu_nios2_signal_handler(int host_signum, void *pinfo, void *puc);
void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUNios2State *env);
@ -229,7 +228,7 @@ void nios2_check_interrupts(CPUNios2State *env);
#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
#define cpu_init(cpu_model) CPU(cpu_nios2_init(cpu_model))
#define cpu_init(cpu_model) cpu_generic_init(TYPE_NIOS2_CPU, cpu_model)
#define cpu_gen_code cpu_nios2_gen_code
#define cpu_signal_handler cpu_nios2_signal_handler

5
target/openrisc/cpu.c
View File

@ -210,11 +210,6 @@ static void openrisc_cpu_register_types(void)
}
}
OpenRISCCPU *cpu_openrisc_init(const char *cpu_model)
{
return OPENRISC_CPU(cpu_generic_init(TYPE_OPENRISC_CPU, cpu_model));
}
/* Sort alphabetically by type name, except for "any". */
static gint openrisc_cpu_list_compare(gconstpointer a, gconstpointer b)
{

4
target/openrisc/cpu.h
View File

@ -347,8 +347,6 @@ static inline OpenRISCCPU *openrisc_env_get_cpu(CPUOpenRISCState *env)
#define ENV_OFFSET offsetof(OpenRISCCPU, env)
OpenRISCCPU *cpu_openrisc_init(const char *cpu_model);
void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf);
void openrisc_cpu_do_interrupt(CPUState *cpu);
bool openrisc_cpu_exec_interrupt(CPUState *cpu, int int_req);
@ -390,7 +388,7 @@ int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu,
int *prot, target_ulong address, int rw);
#endif
#define cpu_init(cpu_model) CPU(cpu_openrisc_init(cpu_model))
#define cpu_init(cpu_model) cpu_generic_init(TYPE_OPENRISC_CPU, cpu_model)
#include "exec/cpu-all.h"

3
target/ppc/cpu.h
View File

@ -1276,7 +1276,6 @@ extern const struct VMStateDescription vmstate_ppc_cpu;
#endif
/*****************************************************************************/
PowerPCCPU *cpu_ppc_init(const char *cpu_model);
void ppc_translate_init(void);
const char *ppc_cpu_lookup_alias(const char *alias);
/* you can call this signal handler from your SIGBUS and SIGSEGV
@ -1353,7 +1352,7 @@ static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
#define cpu_init(cpu_model) CPU(cpu_ppc_init(cpu_model))
#define cpu_init(cpu_model) cpu_generic_init(TYPE_POWERPC_CPU, cpu_model)
#define cpu_signal_handler cpu_ppc_signal_handler
#define cpu_list ppc_cpu_list

5
target/ppc/translate_init.c
View File

@ -10271,11 +10271,6 @@ const char *ppc_cpu_lookup_alias(const char *alias)
return NULL;
}
PowerPCCPU *cpu_ppc_init(const char *cpu_model)
{
return POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU, cpu_model));
}
PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc)
{
ObjectClass *oc = OBJECT_CLASS(pcc);

7
target/s390x/cpu.c
View File

@ -306,6 +306,13 @@ static void s390_cpu_initfn(Object *obj)
inited = true;
s390x_translate_init();
}
#if defined(CONFIG_USER_ONLY)
{
S390CPUClass *scc = S390_CPU_GET_CLASS(obj);
cpu->id = scc->next_cpu_id;
}
#endif
}
static void s390_cpu_finalize(Object *obj)

3
target/s390x/cpu.h
View File

@ -688,8 +688,7 @@ const char *s390_default_cpu_model_name(void);
/* helper.c */
S390CPU *cpu_s390x_init(const char *cpu_model);
#define cpu_init(model) CPU(cpu_s390x_init(model))
#define cpu_init(cpu_model) cpu_generic_init(TYPE_S390_CPU, cpu_model)
S390CPU *s390x_new_cpu(const char *cpu_model, int64_t id, Error **errp);
/* you can call this signal handler from your SIGBUS and SIGSEGV
signal handlers to inform the virtual CPU of exceptions. non zero

14
target/s390x/helper.c
View File

@ -129,20 +129,6 @@ out:
return cpu;
}
S390CPU *cpu_s390x_init(const char *cpu_model)
{
Error *err = NULL;
S390CPU *cpu;
/* Use to track CPU ID for linux-user only */
static int64_t next_cpu_id;
cpu = s390x_new_cpu(cpu_model, next_cpu_id++, &err);
if (err) {
error_report_err(err);
}
return cpu;
}
#ifndef CONFIG_USER_ONLY
hwaddr s390_cpu_get_phys_page_debug(CPUState *cs, vaddr vaddr)

5
target/sh4/cpu.c
View File

@ -156,11 +156,6 @@ static ObjectClass *superh_cpu_class_by_name(const char *cpu_model)
return oc;
}
SuperHCPU *cpu_sh4_init(const char *cpu_model)
{
return SUPERH_CPU(cpu_generic_init(TYPE_SUPERH_CPU, cpu_model));
}
static void sh7750r_cpu_initfn(Object *obj)
{
SuperHCPU *cpu = SUPERH_CPU(obj);

3
target/sh4/cpu.h
View File

@ -238,7 +238,6 @@ void superh_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
int mmu_idx, uintptr_t retaddr);
void sh4_translate_init(void);
SuperHCPU *cpu_sh4_init(const char *cpu_model);
int cpu_sh4_signal_handler(int host_signum, void *pinfo,
void *puc);
int superh_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
@ -269,7 +268,7 @@ int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr);
void cpu_load_tlb(CPUSH4State * env);
#define cpu_init(cpu_model) CPU(cpu_sh4_init(cpu_model))
#define cpu_init(cpu_model) cpu_generic_init(TYPE_SUPERH_CPU, cpu_model)
#define cpu_signal_handler cpu_sh4_signal_handler
#define cpu_list sh4_cpu_list

2
target/sparc/cpu-qom.h
View File

@ -35,6 +35,7 @@
#define SPARC_CPU_GET_CLASS(obj) \
OBJECT_GET_CLASS(SPARCCPUClass, (obj), TYPE_SPARC_CPU)
typedef struct sparc_def_t sparc_def_t;
/**
* SPARCCPUClass:
* @parent_realize: The parent class' realize handler.
@ -49,6 +50,7 @@ typedef struct SPARCCPUClass {
DeviceRealize parent_realize;
void (*parent_reset)(CPUState *cpu);
sparc_def_t *cpu_def;
} SPARCCPUClass;
typedef struct SPARCCPU SPARCCPU;

397
target/sparc/cpu.c
View File

@ -22,11 +22,11 @@
#include "cpu.h"
#include "qemu/error-report.h"
#include "exec/exec-all.h"
#include "hw/qdev-properties.h"
#include "qapi/visitor.h"
//#define DEBUG_FEATURES
static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model);
/* CPUClass::reset() */
static void sparc_cpu_reset(CPUState *s)
{
@ -68,7 +68,7 @@ static void sparc_cpu_reset(CPUState *s)
env->lsu = 0;
#else
env->mmuregs[0] &= ~(MMU_E | MMU_NF);
env->mmuregs[0] |= env->def->mmu_bm;
env->mmuregs[0] |= env->def.mmu_bm;
#endif
env->pc = 0;
env->npc = env->pc + 4;
@ -104,62 +104,94 @@ static void cpu_sparc_disas_set_info(CPUState *cpu, disassemble_info *info)
#endif
}
static void sparc_cpu_parse_features(CPUState *cs, char *features,
Error **errp);
static int cpu_sparc_register(SPARCCPU *cpu, const char *cpu_model)
static void
cpu_add_feat_as_prop(const char *typename, const char *name, const char *val)
{
CPUSPARCState *env = &cpu->env;
char *s = g_strdup(cpu_model);
char *featurestr, *name = strtok(s, ",");
sparc_def_t def1, *def = &def1;
Error *err = NULL;
if (cpu_sparc_find_by_name(def, name) < 0) {
g_free(s);
return -1;
}
env->def = g_memdup(def, sizeof(*def));
featurestr = strtok(NULL, ",");
sparc_cpu_parse_features(CPU(cpu), featurestr, &err);
g_free(s);
if (err) {
error_report_err(err);
return -1;
}
env->version = def->iu_version;
env->fsr = def->fpu_version;
env->nwindows = def->nwindows;
#if !defined(TARGET_SPARC64)
env->mmuregs[0] |= def->mmu_version;
cpu_sparc_set_id(env, 0);
env->mxccregs[7] |= def->mxcc_version;
#else
env->mmu_version = def->mmu_version;
env->maxtl = def->maxtl;
env->version |= def->maxtl << 8;
env->version |= def->nwindows - 1;
#endif
return 0;
GlobalProperty *prop = g_new0(typeof(*prop), 1);
prop->driver = typename;
prop->property = g_strdup(name);
prop->value = g_strdup(val);
prop->errp = &error_fatal;
qdev_prop_register_global(prop);
}
SPARCCPU *cpu_sparc_init(const char *cpu_model)
/* Parse "+feature,-feature,feature=foo" CPU feature string */
static void sparc_cpu_parse_features(const char *typename, char *features,
Error **errp)
{
SPARCCPU *cpu;
GList *l, *plus_features = NULL, *minus_features = NULL;
char *featurestr; /* Single 'key=value" string being parsed */
static bool cpu_globals_initialized;
cpu = SPARC_CPU(object_new(TYPE_SPARC_CPU));
if (cpu_globals_initialized) {
return;
}
cpu_globals_initialized = true;
if (cpu_sparc_register(cpu, cpu_model) < 0) {
object_unref(OBJECT(cpu));
return NULL;
if (!features) {
return;
}
object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
for (featurestr = strtok(features, ",");
featurestr;
featurestr = strtok(NULL, ",")) {
const char *name;
const char *val = NULL;
char *eq = NULL;
return cpu;
/* Compatibility syntax: */
if (featurestr[0] == '+') {
plus_features = g_list_append(plus_features,
g_strdup(featurestr + 1));
continue;
} else if (featurestr[0] == '-') {
minus_features = g_list_append(minus_features,
g_strdup(featurestr + 1));
continue;
}
eq = strchr(featurestr, '=');
name = featurestr;
if (eq) {
*eq++ = 0;
val = eq;
/*
* Temporarily, only +feat/-feat will be supported
* for boolean properties until we remove the
* minus-overrides-plus semantics and just follow
* the order options appear on the command-line.
*
* TODO: warn if user is relying on minus-override-plus semantics
* TODO: remove minus-override-plus semantics after
* warning for a few releases
*/
if (!strcasecmp(val, "on") ||
!strcasecmp(val, "off") ||
!strcasecmp(val, "true") ||
!strcasecmp(val, "false")) {
error_setg(errp, "Boolean properties in format %s=%s"
" are not supported", name, val);
return;
}
} else {
error_setg(errp, "Unsupported property format: %s", name);
return;
}
cpu_add_feat_as_prop(typename, name, val);
}
for (l = plus_features; l; l = l->next) {
const char *name = l->data;
cpu_add_feat_as_prop(typename, name, "on");
}
g_list_free_full(plus_features, g_free);
for (l = minus_features; l; l = l->next) {
const char *name = l->data;
cpu_add_feat_as_prop(typename, name, "off");
}
g_list_free_full(minus_features, g_free);
}
void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu)
@ -540,124 +572,6 @@ static void print_features(FILE *f, fprintf_function cpu_fprintf,
}
}
static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features)
{
unsigned int i;
for (i = 0; i < ARRAY_SIZE(feature_name); i++) {
if (feature_name[i] && !strcmp(flagname, feature_name[i])) {
*features |= 1 << i;
return;
}
}
error_report("CPU feature %s not found", flagname);
}
static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *name)
{
unsigned int i;
const sparc_def_t *def = NULL;
for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) {
if (strcasecmp(name, sparc_defs[i].name) == 0) {
def = &sparc_defs[i];
}
}
if (!def) {
return -1;
}
memcpy(cpu_def, def, sizeof(*def));
return 0;
}
static void sparc_cpu_parse_features(CPUState *cs, char *features,
Error **errp)
{
SPARCCPU *cpu = SPARC_CPU(cs);
sparc_def_t *cpu_def = cpu->env.def;
char *featurestr;
uint32_t plus_features = 0;
uint32_t minus_features = 0;
uint64_t iu_version;
uint32_t fpu_version, mmu_version, nwindows;
featurestr = features ? strtok(features, ",") : NULL;
while (featurestr) {
char *val;
if (featurestr[0] == '+') {
add_flagname_to_bitmaps(featurestr + 1, &plus_features);
} else if (featurestr[0] == '-') {
add_flagname_to_bitmaps(featurestr + 1, &minus_features);
} else if ((val = strchr(featurestr, '='))) {
*val = 0; val++;
if (!strcmp(featurestr, "iu_version")) {
char *err;
iu_version = strtoll(val, &err, 0);
if (!*val || *err) {
error_setg(errp, "bad numerical value %s", val);
return;
}
cpu_def->iu_version = iu_version;
#ifdef DEBUG_FEATURES
fprintf(stderr, "iu_version %" PRIx64 "\n", iu_version);
#endif
} else if (!strcmp(featurestr, "fpu_version")) {
char *err;
fpu_version = strtol(val, &err, 0);
if (!*val || *err) {
error_setg(errp, "bad numerical value %s", val);
return;
}
cpu_def->fpu_version = fpu_version;
#ifdef DEBUG_FEATURES
fprintf(stderr, "fpu_version %x\n", fpu_version);
#endif
} else if (!strcmp(featurestr, "mmu_version")) {
char *err;
mmu_version = strtol(val, &err, 0);
if (!*val || *err) {
error_setg(errp, "bad numerical value %s", val);
return;
}
cpu_def->mmu_version = mmu_version;
#ifdef DEBUG_FEATURES
fprintf(stderr, "mmu_version %x\n", mmu_version);
#endif
} else if (!strcmp(featurestr, "nwindows")) {
char *err;
nwindows = strtol(val, &err, 0);
if (!*val || *err || nwindows > MAX_NWINDOWS ||
nwindows < MIN_NWINDOWS) {
error_setg(errp, "bad numerical value %s", val);
return;
}
cpu_def->nwindows = nwindows;
#ifdef DEBUG_FEATURES
fprintf(stderr, "nwindows %d\n", nwindows);
#endif
} else {
error_setg(errp, "unrecognized feature %s", featurestr);
return;
}
} else {
error_setg(errp, "feature string `%s' not in format "
"(+feature|-feature|feature=xyz)", featurestr);
return;
}
featurestr = strtok(NULL, ",");
}
cpu_def->features |= plus_features;
cpu_def->features &= ~minus_features;
#ifdef DEBUG_FEATURES
print_features(stderr, fprintf, cpu_def->features, NULL);
#endif
}
void sparc_cpu_list(FILE *f, fprintf_function cpu_fprintf)
{
unsigned int i;
@ -796,20 +710,64 @@ static bool sparc_cpu_has_work(CPUState *cs)
cpu_interrupts_enabled(env);
}
static char *sparc_cpu_type_name(const char *cpu_model)
{
char *name = g_strdup_printf("%s-" TYPE_SPARC_CPU, cpu_model);
char *s = name;
/* SPARC cpu model names happen to have whitespaces,
* as type names shouldn't have spaces replace them with '-'
*/
while ((s = strchr(s, ' '))) {
*s = '-';
}
return name;
}
static ObjectClass *sparc_cpu_class_by_name(const char *cpu_model)
{
ObjectClass *oc;
char *typename;
if (cpu_model == NULL) {
return NULL;
}
typename = sparc_cpu_type_name(cpu_model);
oc = object_class_by_name(typename);
g_free(typename);
return oc;
}
static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(dev);
Error *local_err = NULL;
#if defined(CONFIG_USER_ONLY)
SPARCCPU *cpu = SPARC_CPU(dev);
CPUSPARCState *env = &cpu->env;
if ((env->def->features & CPU_FEATURE_FLOAT)) {
env->def->features |= CPU_FEATURE_FLOAT128;
#if defined(CONFIG_USER_ONLY)
if ((env->def.features & CPU_FEATURE_FLOAT)) {
env->def.features |= CPU_FEATURE_FLOAT128;
}
#endif
env->version = env->def.iu_version;
env->fsr = env->def.fpu_version;
env->nwindows = env->def.nwindows;
#if !defined(TARGET_SPARC64)
env->mmuregs[0] |= env->def.mmu_version;
cpu_sparc_set_id(env, 0);
env->mxccregs[7] |= env->def.mxcc_version;
#else
env->mmu_version = env->def.mmu_version;
env->maxtl = env->def.maxtl;
env->version |= env->def.maxtl << 8;
env->version |= env->def.nwindows - 1;
#endif
cpu_exec_realizefn(cs, &local_err);
if (local_err != NULL) {
error_propagate(errp, local_err);
@ -825,6 +783,7 @@ static void sparc_cpu_initfn(Object *obj)
{
CPUState *cs = CPU(obj);
SPARCCPU *cpu = SPARC_CPU(obj);
SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(obj);
CPUSPARCState *env = &cpu->env;
cs->env_ptr = env;
@ -832,16 +791,75 @@ static void sparc_cpu_initfn(Object *obj)
if (tcg_enabled()) {
gen_intermediate_code_init(env);
}
if (scc->cpu_def) {
env->def = *scc->cpu_def;
}
}
static void sparc_cpu_uninitfn(Object *obj)
static void sparc_get_nwindows(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)
{
SPARCCPU *cpu = SPARC_CPU(obj);
CPUSPARCState *env = &cpu->env;
int64_t value = cpu->env.def.nwindows;
g_free(env->def);
visit_type_int(v, name, &value, errp);
}
static void sparc_set_nwindows(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)
{
const int64_t min = MIN_NWINDOWS;
const int64_t max = MAX_NWINDOWS;
SPARCCPU *cpu = SPARC_CPU(obj);
Error *err = NULL;
int64_t value;
visit_type_int(v, name, &value, &err);
if (err) {
error_propagate(errp, err);
return;
}
if (value < min || value > max) {
error_setg(errp, "Property %s.%s doesn't take value %" PRId64
" (minimum: %" PRId64 ", maximum: %" PRId64 ")",
object_get_typename(obj), name ? name : "null",
value, min, max);
return;
}
cpu->env.def.nwindows = value;
}
static PropertyInfo qdev_prop_nwindows = {
.name = "int",
.get = sparc_get_nwindows,
.set = sparc_set_nwindows,
};
static Property sparc_cpu_properties[] = {
DEFINE_PROP_BIT("float", SPARCCPU, env.def.features, 0, false),
DEFINE_PROP_BIT("float128", SPARCCPU, env.def.features, 1, false),
DEFINE_PROP_BIT("swap", SPARCCPU, env.def.features, 2, false),
DEFINE_PROP_BIT("mul", SPARCCPU, env.def.features, 3, false),
DEFINE_PROP_BIT("div", SPARCCPU, env.def.features, 4, false),
DEFINE_PROP_BIT("flush", SPARCCPU, env.def.features, 5, false),
DEFINE_PROP_BIT("fsqrt", SPARCCPU, env.def.features, 6, false),
DEFINE_PROP_BIT("fmul", SPARCCPU, env.def.features, 7, false),
DEFINE_PROP_BIT("vis1", SPARCCPU, env.def.features, 8, false),
DEFINE_PROP_BIT("vis2", SPARCCPU, env.def.features, 9, false),
DEFINE_PROP_BIT("fsmuld", SPARCCPU, env.def.features, 10, false),
DEFINE_PROP_BIT("hypv", SPARCCPU, env.def.features, 11, false),
DEFINE_PROP_BIT("cmt", SPARCCPU, env.def.features, 12, false),
DEFINE_PROP_BIT("gl", SPARCCPU, env.def.features, 13, false),
DEFINE_PROP_UNSIGNED("iu-version", SPARCCPU, env.def.iu_version, 0,
qdev_prop_uint64, target_ulong),
DEFINE_PROP_UINT32("fpu-version", SPARCCPU, env.def.fpu_version, 0),
DEFINE_PROP_UINT32("mmu-version", SPARCCPU, env.def.mmu_version, 0),
{ .name = "nwindows", .info = &qdev_prop_nwindows },
DEFINE_PROP_END_OF_LIST()
};
static void sparc_cpu_class_init(ObjectClass *oc, void *data)
{
SPARCCPUClass *scc = SPARC_CPU_CLASS(oc);
@ -850,10 +868,13 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
scc->parent_realize = dc->realize;
dc->realize = sparc_cpu_realizefn;
dc->props = sparc_cpu_properties;
scc->parent_reset = cc->reset;
cc->reset = sparc_cpu_reset;
cc->class_by_name = sparc_cpu_class_by_name;
cc->parse_features = sparc_cpu_parse_features;
cc->has_work = sparc_cpu_has_work;
cc->do_interrupt = sparc_cpu_do_interrupt;
cc->cpu_exec_interrupt = sparc_cpu_exec_interrupt;
@ -887,15 +908,39 @@ static const TypeInfo sparc_cpu_type_info = {
.parent = TYPE_CPU,
.instance_size = sizeof(SPARCCPU),
.instance_init = sparc_cpu_initfn,
.instance_finalize = sparc_cpu_uninitfn,
.abstract = false,
.abstract = true,
.class_size = sizeof(SPARCCPUClass),
.class_init = sparc_cpu_class_init,
};
static void sparc_cpu_cpudef_class_init(ObjectClass *oc, void *data)
{
SPARCCPUClass *scc = SPARC_CPU_CLASS(oc);
scc->cpu_def = data;
}
static void sparc_register_cpudef_type(const struct sparc_def_t *def)
{
char *typename = sparc_cpu_type_name(def->name);
TypeInfo ti = {
.name = typename,
.parent = TYPE_SPARC_CPU,
.class_init = sparc_cpu_cpudef_class_init,
.class_data = (void *)def,
};
type_register(&ti);
g_free(typename);
}
static void sparc_cpu_register_types(void)
{
int i;
type_register_static(&sparc_cpu_type_info);
for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) {
sparc_register_cpudef_type(&sparc_defs[i]);
}
}
type_init(sparc_cpu_register_types)

11
target/sparc/cpu.h
View File

@ -529,7 +529,7 @@ struct CPUSPARCState {
#define SOFTINT_INTRMASK (0xFFFE)
#define SOFTINT_REG_MASK (SOFTINT_STIMER|SOFTINT_INTRMASK|SOFTINT_TIMER)
#endif
sparc_def_t *def;
sparc_def_t def;
void *irq_manager;
void (*qemu_irq_ack)(CPUSPARCState *env, void *irq_manager, int intno);
@ -579,7 +579,6 @@ void cpu_raise_exception_ra(CPUSPARCState *, int, uintptr_t) QEMU_NORETURN;
#ifndef NO_CPU_IO_DEFS
/* cpu_init.c */
SPARCCPU *cpu_sparc_init(const char *cpu_model);
void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu);
void sparc_cpu_list(FILE *f, fprintf_function cpu_fprintf);
/* mmu_helper.c */
@ -656,7 +655,7 @@ hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr,
int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
#ifndef NO_CPU_IO_DEFS
#define cpu_init(cpu_model) CPU(cpu_sparc_init(cpu_model))
#define cpu_init(cpu_model) cpu_generic_init(TYPE_SPARC_CPU, cpu_model)
#endif
#define cpu_signal_handler cpu_sparc_signal_handler
@ -679,7 +678,7 @@ int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
#if defined (TARGET_SPARC64)
static inline int cpu_has_hypervisor(CPUSPARCState *env1)
{
return env1->def->features & CPU_FEATURE_HYPV;
return env1->def.features & CPU_FEATURE_HYPV;
}
static inline int cpu_hypervisor_mode(CPUSPARCState *env1)
@ -788,14 +787,14 @@ static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, target_ulong *pc,
if (env->pstate & PS_AM) {
flags |= TB_FLAG_AM_ENABLED;
}
if ((env->def->features & CPU_FEATURE_FLOAT)
if ((env->def.features & CPU_FEATURE_FLOAT)
&& (env->pstate & PS_PEF)
&& (env->fprs & FPRS_FEF)) {
flags |= TB_FLAG_FPU_ENABLED;
}
flags |= env->asi << TB_FLAG_ASI_SHIFT;
#else
if ((env->def->features & CPU_FEATURE_FLOAT) && env->psref) {
if ((env->def.features & CPU_FEATURE_FLOAT) && env->psref) {
flags |= TB_FLAG_FPU_ENABLED;
}
#endif

2
target/sparc/int32_helper.c
View File

@ -108,7 +108,7 @@ void sparc_cpu_do_interrupt(CPUState *cs)
#if !defined(CONFIG_USER_ONLY)
if (env->psret == 0) {
if (cs->exception_index == 0x80 &&
env->def->features & CPU_FEATURE_TA0_SHUTDOWN) {
env->def.features & CPU_FEATURE_TA0_SHUTDOWN) {
qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
} else {
cpu_abort(cs, "Trap 0x%02x while interrupts disabled, Error state",

2
target/sparc/int64_helper.c
View File

@ -147,7 +147,7 @@ void sparc_cpu_do_interrupt(CPUState *cs)
}
}
if (env->def->features & CPU_FEATURE_GL) {
if (env->def.features & CPU_FEATURE_GL) {
tsptr->tstate |= (env->gl & 7ULL) << 40;
cpu_gl_switch_gregs(env, env->gl + 1);
env->gl++;

14
target/sparc/ldst_helper.c
View File

@ -513,7 +513,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr,
case 0x00: /* Leon3 Cache Control */
case 0x08: /* Leon3 Instruction Cache config */
case 0x0C: /* Leon3 Date Cache config */
if (env->def->features & CPU_FEATURE_CACHE_CTRL) {
if (env->def.features & CPU_FEATURE_CACHE_CTRL) {
ret = leon3_cache_control_ld(env, addr, size);
}
break;
@ -736,7 +736,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val,
case 0x00: /* Leon3 Cache Control */
case 0x08: /* Leon3 Instruction Cache config */
case 0x0C: /* Leon3 Date Cache config */
if (env->def->features & CPU_FEATURE_CACHE_CTRL) {
if (env->def.features & CPU_FEATURE_CACHE_CTRL) {
leon3_cache_control_st(env, addr, val, size);
}
break;
@ -904,15 +904,15 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val,
/* Mappings generated during no-fault mode
are invalid in normal mode. */
if ((oldreg ^ env->mmuregs[reg])
& (MMU_NF | env->def->mmu_bm)) {
& (MMU_NF | env->def.mmu_bm)) {
tlb_flush(CPU(cpu));
}
break;
case 1: /* Context Table Pointer Register */
env->mmuregs[reg] = val & env->def->mmu_ctpr_mask;
env->mmuregs[reg] = val & env->def.mmu_ctpr_mask;
break;
case 2: /* Context Register */
env->mmuregs[reg] = val & env->def->mmu_cxr_mask;
env->mmuregs[reg] = val & env->def.mmu_cxr_mask;
if (oldreg != env->mmuregs[reg]) {
/* we flush when the MMU context changes because
QEMU has no MMU context support */
@ -923,11 +923,11 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val,
case 4: /* Synchronous Fault Address Register */
break;
case 0x10: /* TLB Replacement Control Register */
env->mmuregs[reg] = val & env->def->mmu_trcr_mask;
env->mmuregs[reg] = val & env->def.mmu_trcr_mask;
break;
case 0x13: /* Synchronous Fault Status Register with Read
and Clear */
env->mmuregs[3] = val & env->def->mmu_sfsr_mask;
env->mmuregs[3] = val & env->def.mmu_sfsr_mask;
break;
case 0x14: /* Synchronous Fault Address Register */
env->mmuregs[4] = val;

2
target/sparc/mmu_helper.c
View File

@ -95,7 +95,7 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
if (mmu_idx == MMU_PHYS_IDX) {
*page_size = TARGET_PAGE_SIZE;
/* Boot mode: instruction fetches are taken from PROM */
if (rw == 2 && (env->mmuregs[0] & env->def->mmu_bm)) {
if (rw == 2 && (env->mmuregs[0] & env->def.mmu_bm)) {
*physical = env->prom_addr | (address & 0x7ffffULL);
*prot = PAGE_READ | PAGE_EXEC;
return 0;

2
target/sparc/translate.c
View File

@ -5756,7 +5756,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock * tb)
dc->npc = (target_ulong) tb->cs_base;
dc->cc_op = CC_OP_DYNAMIC;
dc->mem_idx = tb->flags & TB_FLAG_MMU_MASK;
dc->def = env->def;
dc->def = &env->def;
dc->fpu_enabled = tb_fpu_enabled(tb->flags);
dc->address_mask_32bit = tb_am_enabled(tb->flags);
dc->singlestep = (cs->singlestep_enabled || singlestep);

4
target/sparc/win_helper.c
View File

@ -295,7 +295,7 @@ void helper_wrcwp(CPUSPARCState *env, target_ulong new_cwp)
static inline uint64_t *get_gregset(CPUSPARCState *env, uint32_t pstate)
{
if (env->def->features & CPU_FEATURE_GL) {
if (env->def.features & CPU_FEATURE_GL) {
return env->glregs + (env->gl & 7) * 8;
}
@ -343,7 +343,7 @@ void cpu_change_pstate(CPUSPARCState *env, uint32_t new_pstate)
uint32_t pstate_regs, new_pstate_regs;
uint64_t *src, *dst;
if (env->def->features & CPU_FEATURE_GL) {
if (env->def.features & CPU_FEATURE_GL) {
/* PS_AG, IG and MG are not implemented in this case */
new_pstate &= ~(PS_AG | PS_IG | PS_MG);
env->pstate = new_pstate;

11
target/tilegx/cpu.c
View File

@ -52,15 +52,9 @@ static void tilegx_cpu_dump_state(CPUState *cs, FILE *f,
env->pc, env->spregs[TILEGX_SPR_CMPEXCH]);
}
TileGXCPU *cpu_tilegx_init(const char *cpu_model)
static ObjectClass *tilegx_cpu_class_by_name(const char *cpu_model)
{
TileGXCPU *cpu;
cpu = TILEGX_CPU(object_new(TYPE_TILEGX_CPU));
object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
return cpu;
return object_class_by_name(TYPE_TILEGX_CPU);
}
static void tilegx_cpu_set_pc(CPUState *cs, vaddr value)
@ -159,6 +153,7 @@ static void tilegx_cpu_class_init(ObjectClass *oc, void *data)
tcc->parent_reset = cc->reset;
cc->reset = tilegx_cpu_reset;
cc->class_by_name = tilegx_cpu_class_by_name;
cc->has_work = tilegx_cpu_has_work;
cc->do_interrupt = tilegx_cpu_do_interrupt;
cc->cpu_exec_interrupt = tilegx_cpu_exec_interrupt;

4
target/tilegx/cpu.h
View File

@ -164,9 +164,7 @@ static inline TileGXCPU *tilegx_env_get_cpu(CPUTLGState *env)
void tilegx_tcg_init(void);
int cpu_tilegx_signal_handler(int host_signum, void *pinfo, void *puc);
TileGXCPU *cpu_tilegx_init(const char *cpu_model);
#define cpu_init(cpu_model) CPU(cpu_tilegx_init(cpu_model))
#define cpu_init(cpu_model) cpu_generic_init(TYPE_TILEGX_CPU, cpu_model)
#define cpu_signal_handler cpu_tilegx_signal_handler

4
target/tricore/cpu.h
View File

@ -411,9 +411,7 @@ static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, target_ulong *pc,
*flags = 0;
}
TriCoreCPU *cpu_tricore_init(const char *cpu_model);
#define cpu_init(cpu_model) CPU(cpu_tricore_init(cpu_model))
#define cpu_init(cpu_model) cpu_generic_init(TYPE_TRICORE_CPU, cpu_model)
/* helpers.c */

5
target/tricore/helper.c
View File

@ -78,11 +78,6 @@ int cpu_tricore_handle_mmu_fault(CPUState *cs, target_ulong address,
return ret;
}
TriCoreCPU *cpu_tricore_init(const char *cpu_model)
{
return TRICORE_CPU(cpu_generic_init(TYPE_TRICORE_CPU, cpu_model));
}
static void tricore_cpu_list_entry(gpointer data, gpointer user_data)
{
ObjectClass *oc = data;

4
target/unicore32/cpu.h
View File

@ -165,9 +165,7 @@ static inline int cpu_mmu_index(CPUUniCore32State *env, bool ifetch)
#include "exec/cpu-all.h"
UniCore32CPU *uc32_cpu_init(const char *cpu_model);
#define cpu_init(cpu_model) CPU(uc32_cpu_init(cpu_model))
#define cpu_init(cpu_model) cpu_generic_init(TYPE_UNICORE32_CPU, cpu_model)
static inline void cpu_get_tb_cpu_state(CPUUniCore32State *env, target_ulong *pc,
target_ulong *cs_base, uint32_t *flags)

5
target/unicore32/helper.c
View File

@ -27,11 +27,6 @@
#define DPRINTF(fmt, ...) do {} while (0)
#endif
UniCore32CPU *uc32_cpu_init(const char *cpu_model)
{
return UNICORE32_CPU(cpu_generic_init(TYPE_UNICORE32_CPU, cpu_model));
}
#ifndef CONFIG_USER_ONLY
void helper_cp0_set(CPUUniCore32State *env, uint32_t val, uint32_t creg,
uint32_t cop)

3
target/xtensa/cpu.c
View File

@ -100,9 +100,12 @@ static ObjectClass *xtensa_cpu_class_by_name(const char *cpu_model)
static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
XtensaCPU *cpu = XTENSA_CPU(dev);
XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(dev);
Error *local_err = NULL;
xtensa_irq_init(&cpu->env);
cpu_exec_realizefn(cs, &local_err);
if (local_err != NULL) {
error_propagate(errp, local_err);

4
target/xtensa/cpu.h
View File

@ -475,9 +475,7 @@ void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
#define XTENSA_DEFAULT_CPU_MODEL "dc232b"
#endif
XtensaCPU *cpu_xtensa_init(const char *cpu_model);
#define cpu_init(cpu_model) CPU(cpu_xtensa_init(cpu_model))
#define cpu_init(cpu_model) cpu_generic_init(TYPE_XTENSA_CPU, cpu_model)
void xtensa_translate_init(void);
void xtensa_breakpoint_handler(CPUState *cs);

22
target/xtensa/helper.c
View File

@ -113,28 +113,6 @@ void xtensa_breakpoint_handler(CPUState *cs)
}
}
XtensaCPU *cpu_xtensa_init(const char *cpu_model)
{
ObjectClass *oc;
XtensaCPU *cpu;
CPUXtensaState *env;
oc = cpu_class_by_name(TYPE_XTENSA_CPU, cpu_model);
if (oc == NULL) {
return NULL;
}
cpu = XTENSA_CPU(object_new(object_class_get_name(oc)));
env = &cpu->env;
xtensa_irq_init(env);
object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
return cpu;
}
void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf)
{
XtensaConfigList *core = xtensa_cores;