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target/arm: Implement ID_MMFR5
In Armv8.6 a new AArch32 ID register ID_MMFR5 is defined. Implement this; we want to be able to use it to report to the guest that we implement FEAT_ETS. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220819110052.2942289-4-peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -975,6 +975,7 @@ struct ArchCPU {
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uint32_t id_mmfr2;
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uint32_t id_mmfr2;
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uint32_t id_mmfr3;
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uint32_t id_mmfr3;
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uint32_t id_mmfr4;
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uint32_t id_mmfr4;
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uint32_t id_mmfr5;
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uint32_t id_pfr0;
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uint32_t id_pfr0;
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uint32_t id_pfr1;
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uint32_t id_pfr1;
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uint32_t id_pfr2;
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uint32_t id_pfr2;
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@ -7586,11 +7586,11 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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.access = PL1_R, .type = ARM_CP_CONST,
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.access = PL1_R, .type = ARM_CP_CONST,
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.accessfn = access_aa64_tid3,
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.accessfn = access_aa64_tid3,
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.resetvalue = 0 },
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.resetvalue = 0 },
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{ .name = "RES_0_C0_C3_6", .state = ARM_CP_STATE_BOTH,
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{ .name = "ID_MMFR5", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6,
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.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6,
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.access = PL1_R, .type = ARM_CP_CONST,
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.access = PL1_R, .type = ARM_CP_CONST,
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.accessfn = access_aa64_tid3,
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.accessfn = access_aa64_tid3,
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.resetvalue = 0 },
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.resetvalue = cpu->isar.id_mmfr5 },
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{ .name = "RES_0_C0_C3_7", .state = ARM_CP_STATE_BOTH,
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{ .name = "RES_0_C0_C3_7", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 7,
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.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 7,
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.access = PL1_R, .type = ARM_CP_CONST,
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.access = PL1_R, .type = ARM_CP_CONST,
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@ -643,6 +643,8 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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ARM64_SYS_REG(3, 0, 0, 3, 2));
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ARM64_SYS_REG(3, 0, 0, 3, 2));
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err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr2,
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err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr2,
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ARM64_SYS_REG(3, 0, 0, 3, 4));
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ARM64_SYS_REG(3, 0, 0, 3, 4));
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err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr5,
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ARM64_SYS_REG(3, 0, 0, 3, 6));
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/*
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/*
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* DBGDIDR is a bit complicated because the kernel doesn't
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* DBGDIDR is a bit complicated because the kernel doesn't
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