From 31dbcff713aa297033a008b5188fbb37abf85f36 Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Mon, 18 Oct 2021 14:32:00 +1000 Subject: [PATCH] target/riscv: Remove some unused macros MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since commit 1a9540d1f1a ("target/riscv: Drop support for ISA spec version 1.09.1") these definitions are unused, remove them. Signed-off-by: Alistair Francis Reviewed-by: Frank Chang Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Bin Meng Message-id: f4d8a7a035f39c0a35d44c1e371c5c99cc2fa15a.1634531504.git.alistair.francis@wdc.com --- target/riscv/cpu_bits.h | 8 -------- 1 file changed, 8 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 999187a9ee..3aa2512d13 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -427,14 +427,6 @@ #define SATP64_ASID 0x0FFFF00000000000ULL #define SATP64_PPN 0x00000FFFFFFFFFFFULL -/* VM modes (mstatus.vm) privileged ISA 1.9.1 */ -#define VM_1_09_MBARE 0 -#define VM_1_09_MBB 1 -#define VM_1_09_MBBID 2 -#define VM_1_09_SV32 8 -#define VM_1_09_SV39 9 -#define VM_1_09_SV48 10 - /* VM modes (satp.mode) privileged ISA 1.10 */ #define VM_1_10_MBARE 0 #define VM_1_10_SV32 1