mirror of https://github.com/xemu-project/xemu.git
tcg: fix build on 32-bit hppa, ppc and sparc hosts
The qemu_ld32s op is only defined if TCG_TARGET_REG_BITS == 64. Signed-off-by: Jay Foad <jay.foad@gmail.com> Signed-off-by: malc <av1474@comtv.ru>
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@ -936,7 +936,6 @@ static const TCGTargetOpDef hppa_op_defs[] = {
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{ INDEX_op_qemu_ld16u, { "r", "L", "L" } },
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{ INDEX_op_qemu_ld16s, { "r", "L", "L" } },
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{ INDEX_op_qemu_ld32u, { "r", "L", "L" } },
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{ INDEX_op_qemu_ld32s, { "r", "L", "L" } },
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{ INDEX_op_qemu_ld64, { "r", "r", "L", "L" } },
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{ INDEX_op_qemu_st8, { "L", "L", "L" } },
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@ -1693,7 +1693,6 @@ static const TCGTargetOpDef ppc_op_defs[] = {
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{ INDEX_op_qemu_ld16u, { "r", "L" } },
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{ INDEX_op_qemu_ld16s, { "r", "L" } },
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{ INDEX_op_qemu_ld32u, { "r", "L" } },
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{ INDEX_op_qemu_ld32s, { "r", "L" } },
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{ INDEX_op_qemu_ld64, { "r", "r", "L" } },
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{ INDEX_op_qemu_st8, { "K", "K" } },
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@ -1706,7 +1705,6 @@ static const TCGTargetOpDef ppc_op_defs[] = {
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{ INDEX_op_qemu_ld16u, { "r", "L", "L" } },
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{ INDEX_op_qemu_ld16s, { "r", "L", "L" } },
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{ INDEX_op_qemu_ld32u, { "r", "L", "L" } },
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{ INDEX_op_qemu_ld32s, { "r", "L", "L" } },
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{ INDEX_op_qemu_ld64, { "r", "L", "L", "L" } },
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{ INDEX_op_qemu_st8, { "K", "K", "K" } },
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@ -1319,9 +1319,11 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
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case INDEX_op_qemu_ld32u:
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tcg_out_qemu_ld(s, args, 2);
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break;
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#if TCG_TARGET_REG_BITS == 64
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case INDEX_op_qemu_ld32s:
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tcg_out_qemu_ld(s, args, 2 | 4);
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break;
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#endif
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case INDEX_op_qemu_st8:
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tcg_out_qemu_st(s, args, 0);
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break;
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@ -1471,7 +1473,9 @@ static const TCGTargetOpDef sparc_op_defs[] = {
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{ INDEX_op_qemu_ld16u, { "r", "L" } },
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{ INDEX_op_qemu_ld16s, { "r", "L" } },
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{ INDEX_op_qemu_ld32u, { "r", "L" } },
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#if TCG_TARGET_REG_BITS == 64
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{ INDEX_op_qemu_ld32s, { "r", "L" } },
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#endif
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{ INDEX_op_qemu_st8, { "L", "L" } },
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{ INDEX_op_qemu_st16, { "L", "L" } },
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