mirror of https://github.com/xemu-project/xemu.git
target-arm: Move block cache ops to new cp15 framework
Move the v6 optional block cache ops to the new cp15 framework. This includes only providing them on the CPUs which implemented them, rather than the previous blunderbuss approach of making all MCRR instructions on all CPUs act as NOPs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -810,6 +810,19 @@ static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
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/* We never have a a block transfer operation in progress */
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{ .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
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.access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
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/* The cache ops themselves: these all NOP for QEMU */
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{ .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
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.access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
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{ .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
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.access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
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{ .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
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.access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
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{ .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
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.access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
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{ .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
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.access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
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{ .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
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.access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
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REGINFO_SENTINEL
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};
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@ -2451,12 +2451,7 @@ static int disas_cp15_insn(CPUARMState *env, DisasContext *s, uint32_t insn)
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return 1;
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if ((insn & (1 << 25)) == 0) {
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if (insn & (1 << 20)) {
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/* mrrc */
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return 1;
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}
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/* mcrr. Used for block cache operations, so implement as no-op. */
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return 0;
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return 1;
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}
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if ((insn & (1 << 4)) == 0) {
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/* cdp */
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