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target/ppc: Fix THREAD_SIBLING_FOREACH for multi-socket 

The THREAD_SIBLING_FOREACH macro wasn't excluding threads from other
chips. Add chip_index field to the thread state and add a check for the
new field in the macro.

Fixes: b769d4c8f4 ("target/ppc: Add initial flags and helpers for SMT support")
Signed-off-by: Glenn Miles <milesg@linux.ibm.com>
[npiggin: set chip_index for spapr too]
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
This commit is contained in:
Glenn Miles 2024-11-14 15:21:19 -06:00 committed by Nicholas Piggin
parent 96746f7a95
commit 2fc0a78a57
3 changed files with 8 additions and 2 deletions
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2
hw/ppc/pnv_core.c
View File

@ -322,6 +322,8 @@ static void pnv_core_cpu_realize(PnvCore *pc, PowerPCCPU *cpu, Error **errp,
pir_spr->default_value = pir;
tir_spr->default_value = tir;
env->chip_index = pc->chip->chip_id;
if (pc->big_core) {
/* 2 "small cores" get the same core index for SMT operations */
env->core_index = core_hwid >> 1;

1
hw/ppc/spapr_cpu_core.c
View File

@ -313,6 +313,7 @@ static PowerPCCPU *spapr_create_vcpu(SpaprCpuCore *sc, int i, Error **errp)
return NULL;
}
env->chip_index = sc->node_id;
env->core_index = cc->core_id;
cpu->node_id = sc->node_id;

7
target/ppc/cpu.h
View File

@ -1253,6 +1253,7 @@ struct CPUArchState {
/* For SMT processors */
bool has_smt_siblings;
int core_index;
int chip_index;
#if !defined(CONFIG_USER_ONLY)
/* MMU context, only relevant for full system emulation */
@ -1412,8 +1413,10 @@ struct CPUArchState {
#define THREAD_SIBLING_FOREACH(cs, cs_sibling) \
CPU_FOREACH(cs_sibling) \
if (POWERPC_CPU(cs)->env.core_index == \
POWERPC_CPU(cs_sibling)->env.core_index)
if ((POWERPC_CPU(cs)->env.chip_index == \
POWERPC_CPU(cs_sibling)->env.chip_index) && \
(POWERPC_CPU(cs)->env.core_index == \
POWERPC_CPU(cs_sibling)->env.core_index))
#define SET_FIT_PERIOD(a_, b_, c_, d_) \
do { \