mirror of https://github.com/xemu-project/xemu.git
target/sparc: Move FPACK16, FPACKFIX to decodetree
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -344,6 +344,8 @@ FCMPEq 10 000 cc:2 110101 rs1:5 0 0101 0111 rs2:5
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FMULD8SUx16 10 ..... 110110 ..... 0 0011 1000 ..... @r_r_r
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FMULD8ULx16 10 ..... 110110 ..... 0 0011 1001 ..... @r_r_r
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FPACK32 10 ..... 110110 ..... 0 0011 1010 ..... @r_r_r
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FPACK16 10 ..... 110110 00000 0 0011 1011 ..... @r_r2
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FPACKFIX 10 ..... 110110 00000 0 0011 1101 ..... @r_r2
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PDIST 10 ..... 110110 ..... 0 0011 1110 ..... @r_r_r
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FALIGNDATAg 10 ..... 110110 ..... 0 0100 1000 ..... @r_r_r
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@ -756,6 +756,24 @@ static void gen_op_array32(TCGv dst, TCGv src1, TCGv src2)
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tcg_gen_shli_tl(dst, dst, 2);
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}
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static void gen_op_fpack16(TCGv_i32 dst, TCGv_i64 src)
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{
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#ifdef TARGET_SPARC64
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gen_helper_fpack16(dst, cpu_gsr, src);
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#else
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g_assert_not_reached();
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#endif
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}
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static void gen_op_fpackfix(TCGv_i32 dst, TCGv_i64 src)
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{
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#ifdef TARGET_SPARC64
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gen_helper_fpackfix(dst, cpu_gsr, src);
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#else
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g_assert_not_reached();
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#endif
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}
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static void gen_op_fpack32(TCGv_i64 dst, TCGv_i64 src1, TCGv_i64 src2)
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{
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#ifdef TARGET_SPARC64
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@ -4589,6 +4607,26 @@ TRANS(FABSs, ALL, do_ff, a, gen_op_fabss)
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TRANS(FSRCs, VIS1, do_ff, a, tcg_gen_mov_i32)
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TRANS(FNOTs, VIS1, do_ff, a, tcg_gen_not_i32)
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static bool do_fd(DisasContext *dc, arg_r_r *a,
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void (*func)(TCGv_i32, TCGv_i64))
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{
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TCGv_i32 dst;
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TCGv_i64 src;
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if (gen_trap_ifnofpu(dc)) {
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return true;
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}
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dst = gen_dest_fpr_F(dc);
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src = gen_load_fpr_D(dc, a->rs);
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func(dst, src);
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gen_store_fpr_F(dc, a->rd, dst);
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return advance_pc(dc);
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}
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TRANS(FPACK16, VIS1, do_fd, a, gen_op_fpack16)
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TRANS(FPACKFIX, VIS1, do_fd, a, gen_op_fpackfix)
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static bool do_env_ff(DisasContext *dc, arg_r_r *a,
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void (*func)(TCGv_i32, TCGv_env, TCGv_i32))
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{
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@ -5265,10 +5303,9 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
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} else if (xop == 0x36) {
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#ifdef TARGET_SPARC64
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/* VIS */
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TCGv_i64 cpu_src1_64, cpu_dst_64;
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TCGv_i64 cpu_dst_64;
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TCGv_i32 cpu_dst_32;
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int opf = GET_FIELD_SP(insn, 5, 13);
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int rs2 = GET_FIELD(insn, 27, 31);
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int rd = GET_FIELD(insn, 2, 6);
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if (gen_trap_ifnofpu(dc)) {
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@ -5351,21 +5388,9 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
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case 0x02a: /* VIS I fcmpeq16 */
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case 0x02c: /* VIS I fcmpgt32 */
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case 0x02e: /* VIS I fcmpeq32 */
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g_assert_not_reached(); /* in decodetree */
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case 0x03b: /* VIS I fpack16 */
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CHECK_FPU_FEATURE(dc, VIS1);
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cpu_src1_64 = gen_load_fpr_D(dc, rs2);
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cpu_dst_32 = gen_dest_fpr_F(dc);
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gen_helper_fpack16(cpu_dst_32, cpu_gsr, cpu_src1_64);
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gen_store_fpr_F(dc, rd, cpu_dst_32);
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break;
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case 0x03d: /* VIS I fpackfix */
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CHECK_FPU_FEATURE(dc, VIS1);
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cpu_src1_64 = gen_load_fpr_D(dc, rs2);
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cpu_dst_32 = gen_dest_fpr_F(dc);
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gen_helper_fpackfix(cpu_dst_32, cpu_gsr, cpu_src1_64);
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gen_store_fpr_F(dc, rd, cpu_dst_32);
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break;
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g_assert_not_reached(); /* in decodetree */
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case 0x060: /* VIS I fzero */
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CHECK_FPU_FEATURE(dc, VIS1);
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cpu_dst_64 = gen_dest_fpr_D(dc, rd);
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