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target/mips: Style improvements in cp0_timer.c 

Fixes mostly errors and warnings reported by 'checkpatch.pl -f'.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <1566216496-17375-7-git-send-email-aleksandar.markovic@rt-rk.com>
This commit is contained in:
Aleksandar Markovic 2019-08-19 14:07:45 +02:00
parent 50d69ee0d8
commit 2f0d019672
1 changed files with 23 additions and 19 deletions
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42
target/mips/cp0_timer.c
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@ -30,7 +30,7 @@
#define TIMER_PERIOD 10 /* 10 ns period for 100 Mhz frequency */
/* XXX: do not use a global */
uint32_t cpu_mips_get_random (CPUMIPSState *env)
uint32_t cpu_mips_get_random(CPUMIPSState *env)
{
static uint32_t seed = 1;
static uint32_t prev_idx = 0;
@ -43,8 +43,10 @@ uint32_t cpu_mips_get_random (CPUMIPSState *env)
/* Don't return same value twice, so get another value */
do {
/* Use a simple algorithm of Linear Congruential Generator
* from ISO/IEC 9899 standard. */
/*
* Use a simple algorithm of Linear Congruential Generator
* from ISO/IEC 9899 standard.
*/
seed = 1103515245 * seed + 12345;
idx = (seed >> 16) % nb_rand_tlb + env->CP0_Wired;
} while (idx == prev_idx);
@ -74,7 +76,7 @@ static void cpu_mips_timer_expire(CPUMIPSState *env)
qemu_irq_raise(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
}
uint32_t cpu_mips_get_count (CPUMIPSState *env)
uint32_t cpu_mips_get_count(CPUMIPSState *env)
{
if (env->CP0_Cause & (1 << CP0Ca_DC)) {
return env->CP0_Count;
@ -92,16 +94,16 @@ uint32_t cpu_mips_get_count (CPUMIPSState *env)
}
}
void cpu_mips_store_count (CPUMIPSState *env, uint32_t count)
void cpu_mips_store_count(CPUMIPSState *env, uint32_t count)
{
/*
* This gets called from cpu_state_reset(), potentially before timer init.
* So env->timer may be NULL, which is also the case with KVM enabled so
* treat timer as disabled in that case.
*/
if (env->CP0_Cause & (1 << CP0Ca_DC) || !env->timer)
if (env->CP0_Cause & (1 << CP0Ca_DC) || !env->timer) {
env->CP0_Count = count;
else {
} else {
/* Store new count register */
env->CP0_Count = count -
(uint32_t)(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / TIMER_PERIOD);
@ -110,13 +112,15 @@ void cpu_mips_store_count (CPUMIPSState *env, uint32_t count)
}
}
void cpu_mips_store_compare (CPUMIPSState *env, uint32_t value)
void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value)
{
env->CP0_Compare = value;
if (!(env->CP0_Cause & (1 << CP0Ca_DC)))
if (!(env->CP0_Cause & (1 << CP0Ca_DC))) {
cpu_mips_timer_update(env);
if (env->insn_flags & ISA_MIPS32R2)
}
if (env->insn_flags & ISA_MIPS32R2) {
env->CP0_Cause &= ~(1 << CP0Ca_TI);
}
qemu_irq_lower(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
}
@ -132,27 +136,27 @@ void cpu_mips_stop_count(CPUMIPSState *env)
TIMER_PERIOD);
}
static void mips_timer_cb (void *opaque)
static void mips_timer_cb(void *opaque)
{
CPUMIPSState *env;
env = opaque;
#if 0
qemu_log("%s\n", __func__);
#endif
if (env->CP0_Cause & (1 << CP0Ca_DC))
if (env->CP0_Cause & (1 << CP0Ca_DC)) {
return;
}
/* ??? This callback should occur when the counter is exactly equal to
the comparator value. Offset the count by one to avoid immediately
retriggering the callback before any virtual time has passed. */
/*
* ??? This callback should occur when the counter is exactly equal to
* the comparator value. Offset the count by one to avoid immediately
* retriggering the callback before any virtual time has passed.
*/
env->CP0_Count++;
cpu_mips_timer_expire(env);
env->CP0_Count--;
}
void cpu_mips_clock_init (MIPSCPU *cpu)
void cpu_mips_clock_init(MIPSCPU *cpu)
{
CPUMIPSState *env = &cpu->env;