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target/arm: Implement MVE VCVT between fp and integer
Implement the MVE "VCVT (between floating-point and integer)" insn. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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target/arm
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@ -798,3 +798,10 @@ VCVT_UF_fixed 1111 1111 1 . ...... ... 0 11 . 0 01 . 1 ... 0 @vcvt
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VCVT_FS_fixed 1110 1111 1 . ...... ... 0 11 . 1 01 . 1 ... 0 @vcvt
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VCVT_FU_fixed 1111 1111 1 . ...... ... 0 11 . 1 01 . 1 ... 0 @vcvt
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# VCVT between floating point and integer (halfprec and single);
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# VCVT_<from><to>, S = signed int, U = unsigned int, F = float
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VCVT_SF 1111 1111 1 . 11 .. 11 ... 0 011 00 1 . 0 ... 0 @1op
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VCVT_UF 1111 1111 1 . 11 .. 11 ... 0 011 01 1 . 0 ... 0 @1op
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VCVT_FS 1111 1111 1 . 11 .. 11 ... 0 011 10 1 . 0 ... 0 @1op
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VCVT_FU 1111 1111 1 . 11 .. 11 ... 0 011 11 1 . 0 ... 0 @1op
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@ -543,6 +543,38 @@ DO_1OP(VQNEG, vqneg)
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DO_1OP(VMAXA, vmaxa)
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DO_1OP(VMINA, vmina)
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/*
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* For simple float/int conversions we use the fixed-point
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* conversion helpers with a zero shift count
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*/
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#define DO_VCVT(INSN, HFN, SFN) \
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static void gen_##INSN##h(TCGv_ptr env, TCGv_ptr qd, TCGv_ptr qm) \
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{ \
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gen_helper_mve_##HFN(env, qd, qm, tcg_constant_i32(0)); \
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} \
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static void gen_##INSN##s(TCGv_ptr env, TCGv_ptr qd, TCGv_ptr qm) \
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{ \
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gen_helper_mve_##SFN(env, qd, qm, tcg_constant_i32(0)); \
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} \
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static bool trans_##INSN(DisasContext *s, arg_1op *a) \
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{ \
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static MVEGenOneOpFn * const fns[] = { \
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NULL, \
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gen_##INSN##h, \
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gen_##INSN##s, \
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NULL, \
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}; \
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if (!dc_isar_feature(aa32_mve_fp, s)) { \
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return false; \
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} \
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return do_1op(s, a, fns[a->size]); \
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}
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DO_VCVT(VCVT_SF, vcvt_sh, vcvt_sf)
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DO_VCVT(VCVT_UF, vcvt_uh, vcvt_uf)
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DO_VCVT(VCVT_FS, vcvt_hs, vcvt_fs)
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DO_VCVT(VCVT_FU, vcvt_hu, vcvt_fu)
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/* Narrowing moves: only size 0 and 1 are valid */
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#define DO_VMOVN(INSN, FN) \
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static bool trans_##INSN(DisasContext *s, arg_1op *a) \
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