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Special-case iWMMXt register transfer insns, which are in ARM LDC2/STC2 class. 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3107 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
balrog 2007-08-01 02:31:54 +00:00
parent 0e7b8a9f01
commit 2e23213f26
2 changed files with 12 additions and 3 deletions
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8
target-arm/helper.c
View File

@ -838,9 +838,11 @@ void helper_set_cp15(CPUState *env, uint32_t insn, uint32_t val)
case 15: /* Implementation specific. */
if (arm_feature(env, ARM_FEATURE_XSCALE)) {
if (op2 == 0 && crm == 1) {
/* Changes cp0 to cp13 behavior, so needs a TB flush. */
tb_flush(env);
env->cp15.c15_cpar = (val & 0x3fff) | 2;
if (env->cp15.c15_cpar != (val & 0x3fff)) {
/* Changes cp0 to cp13 behavior, so needs a TB flush. */
tb_flush(env);
env->cp15.c15_cpar = val & 0x3fff;
}
break;
}
goto bad_reg;

7
target-arm/translate.c
View File

@ -2230,6 +2230,13 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
gen_op_movl_T0_im(val);
gen_bx(s);
return;
} else if ((insn & 0x0e000f00) == 0x0c000100) {
if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
/* iWMMXt register transfer. */
if (env->cp15.c15_cpar & (1 << 1))
if (!disas_iwmmxt_insn(env, s, insn))
return;
}
} else if ((insn & 0x0fe00000) == 0x0c400000) {
/* Coprocessor double register transfer. */
} else if ((insn & 0x0f000010) == 0x0e000010) {