mirror of https://github.com/xemu-project/xemu.git
acpi: refactor pxb crs computation
Instead of always passing both IO and MEM ranges when computing CRS ranges, define a new CrsRangeSet structure that include them both. This is done before introducing a third type of range, 64-bit MEM, so it will be easier to pass them all around. Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Marcel Apfelbaum <marcel@redhat.com> Tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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@ -751,6 +751,23 @@ static void crs_range_free(gpointer data)
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g_free(entry);
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}
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typedef struct CrsRangeSet {
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GPtrArray *io_ranges;
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GPtrArray *mem_ranges;
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} CrsRangeSet;
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static void crs_range_set_init(CrsRangeSet *range_set)
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{
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range_set->io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
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range_set->mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
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}
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static void crs_range_set_free(CrsRangeSet *range_set)
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{
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g_ptr_array_free(range_set->io_ranges, true);
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g_ptr_array_free(range_set->mem_ranges, true);
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}
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static gint crs_range_compare(gconstpointer a, gconstpointer b)
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{
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CrsRangeEntry *entry_a = *(CrsRangeEntry **)a;
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@ -835,18 +852,17 @@ static void crs_range_merge(GPtrArray *range)
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g_ptr_array_free(tmp, true);
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}
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static Aml *build_crs(PCIHostState *host,
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GPtrArray *io_ranges, GPtrArray *mem_ranges)
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static Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set)
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{
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Aml *crs = aml_resource_template();
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GPtrArray *host_io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
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GPtrArray *host_mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
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CrsRangeSet temp_range_set;
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CrsRangeEntry *entry;
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uint8_t max_bus = pci_bus_num(host->bus);
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uint8_t type;
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int devfn;
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int i;
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crs_range_set_init(&temp_range_set);
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for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) {
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uint64_t range_base, range_limit;
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PCIDevice *dev = host->bus->devices[devfn];
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@ -870,9 +886,11 @@ static Aml *build_crs(PCIHostState *host,
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}
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if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
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crs_range_insert(host_io_ranges, range_base, range_limit);
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crs_range_insert(temp_range_set.io_ranges,
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range_base, range_limit);
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} else { /* "memory" */
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crs_range_insert(host_mem_ranges, range_base, range_limit);
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crs_range_insert(temp_range_set.mem_ranges,
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range_base, range_limit);
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}
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}
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@ -891,7 +909,8 @@ static Aml *build_crs(PCIHostState *host,
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* that do not support multiple root buses
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*/
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if (range_base && range_base <= range_limit) {
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crs_range_insert(host_io_ranges, range_base, range_limit);
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crs_range_insert(temp_range_set.io_ranges,
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range_base, range_limit);
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}
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range_base =
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@ -904,7 +923,8 @@ static Aml *build_crs(PCIHostState *host,
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* that do not support multiple root buses
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*/
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if (range_base && range_base <= range_limit) {
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crs_range_insert(host_mem_ranges, range_base, range_limit);
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crs_range_insert(temp_range_set.mem_ranges,
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range_base, range_limit);
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}
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range_base =
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@ -917,35 +937,36 @@ static Aml *build_crs(PCIHostState *host,
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* that do not support multiple root buses
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*/
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if (range_base && range_base <= range_limit) {
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crs_range_insert(host_mem_ranges, range_base, range_limit);
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crs_range_insert(temp_range_set.mem_ranges,
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range_base, range_limit);
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}
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}
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}
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crs_range_merge(host_io_ranges);
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for (i = 0; i < host_io_ranges->len; i++) {
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entry = g_ptr_array_index(host_io_ranges, i);
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crs_range_merge(temp_range_set.io_ranges);
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for (i = 0; i < temp_range_set.io_ranges->len; i++) {
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entry = g_ptr_array_index(temp_range_set.io_ranges, i);
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aml_append(crs,
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aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
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AML_POS_DECODE, AML_ENTIRE_RANGE,
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0, entry->base, entry->limit, 0,
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entry->limit - entry->base + 1));
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crs_range_insert(io_ranges, entry->base, entry->limit);
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crs_range_insert(range_set->io_ranges, entry->base, entry->limit);
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}
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g_ptr_array_free(host_io_ranges, true);
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crs_range_merge(host_mem_ranges);
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for (i = 0; i < host_mem_ranges->len; i++) {
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entry = g_ptr_array_index(host_mem_ranges, i);
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crs_range_merge(temp_range_set.mem_ranges);
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for (i = 0; i < temp_range_set.mem_ranges->len; i++) {
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entry = g_ptr_array_index(temp_range_set.mem_ranges, i);
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aml_append(crs,
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aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
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AML_MAX_FIXED, AML_NON_CACHEABLE,
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AML_READ_WRITE,
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0, entry->base, entry->limit, 0,
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entry->limit - entry->base + 1));
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crs_range_insert(mem_ranges, entry->base, entry->limit);
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crs_range_insert(range_set->mem_ranges, entry->base, entry->limit);
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}
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g_ptr_array_free(host_mem_ranges, true);
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crs_range_set_free(&temp_range_set);
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aml_append(crs,
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aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
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@ -1902,8 +1923,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
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{
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CrsRangeEntry *entry;
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Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs;
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GPtrArray *mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
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GPtrArray *io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
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CrsRangeSet crs_range_set;
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PCMachineState *pcms = PC_MACHINE(machine);
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PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine);
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uint32_t nr_mem = machine->ram_slots;
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@ -1992,6 +2012,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
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}
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aml_append(dsdt, scope);
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crs_range_set_init(&crs_range_set);
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bus = PC_MACHINE(machine)->bus;
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if (bus) {
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QLIST_FOREACH(bus, &bus->child, sibling) {
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@ -2018,8 +2039,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
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}
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aml_append(dev, build_prt(false));
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crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent),
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io_ranges, mem_ranges);
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crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set);
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aml_append(dev, aml_name_decl("_CRS", crs));
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aml_append(scope, dev);
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aml_append(dsdt, scope);
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@ -2040,9 +2060,9 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
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AML_POS_DECODE, AML_ENTIRE_RANGE,
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0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
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crs_replace_with_free_ranges(io_ranges, 0x0D00, 0xFFFF);
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for (i = 0; i < io_ranges->len; i++) {
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entry = g_ptr_array_index(io_ranges, i);
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crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF);
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for (i = 0; i < crs_range_set.io_ranges->len; i++) {
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entry = g_ptr_array_index(crs_range_set.io_ranges, i);
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aml_append(crs,
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aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
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AML_POS_DECODE, AML_ENTIRE_RANGE,
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@ -2055,11 +2075,11 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
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AML_CACHEABLE, AML_READ_WRITE,
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0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
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crs_replace_with_free_ranges(mem_ranges,
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crs_replace_with_free_ranges(crs_range_set.mem_ranges,
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range_lob(pci_hole),
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range_upb(pci_hole));
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for (i = 0; i < mem_ranges->len; i++) {
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entry = g_ptr_array_index(mem_ranges, i);
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for (i = 0; i < crs_range_set.mem_ranges->len; i++) {
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entry = g_ptr_array_index(crs_range_set.mem_ranges, i);
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aml_append(crs,
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aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
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AML_NON_CACHEABLE, AML_READ_WRITE,
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@ -2094,8 +2114,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
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aml_append(dev, aml_name_decl("_CRS", crs));
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aml_append(scope, dev);
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g_ptr_array_free(io_ranges, true);
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g_ptr_array_free(mem_ranges, true);
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crs_range_set_free(&crs_range_set);
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/* reserve PCIHP resources */
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if (pm->pcihp_io_len) {
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