mirror of https://github.com/xemu-project/xemu.git
hw/sd/sdhci: Fix coding style
Fix coding style issues from checkpatch.pl Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Message-ID: <20241114094839.4128404-2-jamin_lin@aspeedtech.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
This commit is contained in:
Jamin Lin
Philippe Mathieu-Daudé
parent
19e566162c
commit
2df4291956
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@ -233,7 +233,7 @@ static void sdhci_raise_insertion_irq(void *opaque)
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if (s->norintsts & SDHC_NIS_REMOVE) {
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timer_mod(s->insert_timer,
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qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY);
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qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY);
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} else {
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s->prnsts = 0x1ff0000;
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if (s->norintstsen & SDHC_NISEN_INSERT) {
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@ -251,7 +251,7 @@ static void sdhci_set_inserted(DeviceState *dev, bool level)
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if ((s->norintsts & SDHC_NIS_REMOVE) && level) {
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/* Give target some time to notice card ejection */
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timer_mod(s->insert_timer,
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qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY);
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qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY);
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} else {
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if (level) {
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s->prnsts = 0x1ff0000;
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@ -289,9 +289,11 @@ static void sdhci_reset(SDHCIState *s)
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timer_del(s->insert_timer);
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timer_del(s->transfer_timer);
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/* Set all registers to 0. Capabilities/Version registers are not cleared
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/*
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* Set all registers to 0. Capabilities/Version registers are not cleared
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* and assumed to always preserve their value, given to them during
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* initialization */
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* initialization
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*/
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memset(&s->sdmasysad, 0, (uintptr_t)&s->capareg - (uintptr_t)&s->sdmasysad);
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/* Reset other state based on current card insertion/readonly status */
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@ -305,7 +307,8 @@ static void sdhci_reset(SDHCIState *s)
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static void sdhci_poweron_reset(DeviceState *dev)
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{
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/* QOM (ie power-on) reset. This is identical to reset
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/*
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* QOM (ie power-on) reset. This is identical to reset
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* commanded via device register apart from handling of the
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* 'pending insert on powerup' quirk.
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*/
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@ -445,8 +448,10 @@ static void sdhci_read_block_from_card(SDHCIState *s)
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s->prnsts &= ~SDHC_DAT_LINE_ACTIVE;
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}
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/* If stop at block gap request was set and it's not the last block of
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* data - generate Block Event interrupt */
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/*
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* If stop at block gap request was set and it's not the last block of
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* data - generate Block Event interrupt
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*/
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if (s->stopped_state == sdhc_gap_read && (s->trnmod & SDHC_TRNS_MULTI) &&
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s->blkcnt != 1) {
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s->prnsts &= ~SDHC_DAT_LINE_ACTIVE;
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@ -548,8 +553,10 @@ static void sdhci_write_block_to_card(SDHCIState *s)
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sdhci_update_irq(s);
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}
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/* Write @size bytes of @value data to host controller @s Buffer Data Port
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* register */
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/*
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* Write @size bytes of @value data to host controller @s Buffer Data Port
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* register
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*/
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static void sdhci_write_dataport(SDHCIState *s, uint32_t value, unsigned size)
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{
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unsigned i;
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@ -594,9 +601,11 @@ static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s)
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return;
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}
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/* XXX: Some sd/mmc drivers (for example, u-boot-slp) do not account for
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/*
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* XXX: Some sd/mmc drivers (for example, u-boot-slp) do not account for
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* possible stop at page boundary if initial address is not page aligned,
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* allow them to work properly */
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* allow them to work properly
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*/
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if ((s->sdmasysad % boundary_chk) == 0) {
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page_aligned = true;
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}
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@ -702,7 +711,8 @@ static void get_adma_description(SDHCIState *s, ADMADescr *dscr)
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dma_memory_read(s->dma_as, entry_addr, &adma2, sizeof(adma2),
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MEMTXATTRS_UNSPECIFIED);
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adma2 = le64_to_cpu(adma2);
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/* The spec does not specify endianness of descriptor table.
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/*
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* The spec does not specify endianness of descriptor table.
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* We currently assume that it is LE.
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*/
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dscr->addr = (hwaddr)extract64(adma2, 32, 32) & ~0x3ull;
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@ -977,8 +987,10 @@ static bool sdhci_can_issue_command(SDHCIState *s)
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return true;
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}
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/* The Buffer Data Port register must be accessed in sequential and
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* continuous manner */
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/*
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* The Buffer Data Port register must be accessed in sequential and
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* continuous manner
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*/
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static inline bool
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sdhci_buff_access_is_sequential(SDHCIState *s, unsigned byte_num)
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{
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@ -1206,8 +1218,10 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
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MASKED_WRITE(s->argument, mask, value);
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break;
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case SDHC_TRNMOD:
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/* DMA can be enabled only if it is supported as indicated by
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* capabilities register */
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/*
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* DMA can be enabled only if it is supported as indicated by
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* capabilities register
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*/
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if (!(s->capareg & R_SDHC_CAPAB_SDMA_MASK)) {
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value &= ~SDHC_TRNS_DMA;
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}
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@ -1279,8 +1293,10 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
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} else {
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s->norintsts &= ~SDHC_NIS_ERR;
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}
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/* Quirk for Raspberry Pi: pending card insert interrupt
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* appears when first enabled after power on */
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/*
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* Quirk for Raspberry Pi: pending card insert interrupt
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* appears when first enabled after power on
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*/
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if ((s->norintstsen & SDHC_NISEN_INSERT) && s->pending_insert_state) {
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assert(s->pending_insert_quirk);
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s->norintsts |= SDHC_NIS_INSERT;
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@ -1396,8 +1412,10 @@ void sdhci_initfn(SDHCIState *s)
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{
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qbus_init(&s->sdbus, sizeof(s->sdbus), TYPE_SDHCI_BUS, DEVICE(s), "sd-bus");
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s->insert_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_raise_insertion_irq, s);
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s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_data_transfer, s);
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s->insert_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
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sdhci_raise_insertion_irq, s);
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s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
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sdhci_data_transfer, s);
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s->io_ops = &sdhci_mmio_le_ops;
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}
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@ -1445,11 +1463,13 @@ void sdhci_common_realize(SDHCIState *s, Error **errp)
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void sdhci_common_unrealize(SDHCIState *s)
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{
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/* This function is expected to be called only once for each class:
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/*
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* This function is expected to be called only once for each class:
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* - SysBus: via DeviceClass->unrealize(),
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* - PCI: via PCIDeviceClass->exit().
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* However to avoid double-free and/or use-after-free we still nullify
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* this variable (better safe than sorry!). */
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* this variable (better safe than sorry!).
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*/
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g_free(s->fifo_buffer);
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s->fifo_buffer = NULL;
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}
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