From 2dd081ae7642d54470225ea8c3f5cd4ef62fc732 Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Mon, 29 Sep 2014 18:48:50 +0100 Subject: [PATCH] target-arm: A64: Correct updates to FAR and ESR on exceptions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Not all exception types update both FAR and ESR. Reviewed-by: Alex Bennée Reviewed-by: Greg Bellows Signed-off-by: Edgar E. Iglesias Message-id: 1411718914-6608-7-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell --- target-arm/helper-a64.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c index 4be0784c3a..c6ef8e9543 100644 --- a/target-arm/helper-a64.c +++ b/target-arm/helper-a64.c @@ -466,18 +466,17 @@ void aarch64_cpu_do_interrupt(CPUState *cs) env->exception.syndrome); } - env->cp15.esr_el[new_el] = env->exception.syndrome; - env->cp15.far_el[new_el] = env->exception.vaddress; - switch (cs->exception_index) { case EXCP_PREFETCH_ABORT: case EXCP_DATA_ABORT: + env->cp15.far_el[new_el] = env->exception.vaddress; qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n", env->cp15.far_el[new_el]); - break; + /* fall through */ case EXCP_BKPT: case EXCP_UDEF: case EXCP_SWI: + env->cp15.esr_el[new_el] = env->exception.syndrome; break; case EXCP_IRQ: addr += 0x80;