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target/mips/tx79: Introduce PAND/POR/PXOR/PNOR opcodes (parallel logic) 

Introduce the parallel logic opcodes:

 - PAND (Parallel AND)
 - POR  (Parallel OR)
 - PXOR (Parallel XOR)
 - PNOR (Parallel NOR)

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-16-f4bug@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé 2021-02-13 12:24:44 +01:00
parent 64e7392047
commit 2d4ab117be
2 changed files with 58 additions and 0 deletions
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4
target/mips/tcg/tx79.decode
View File

@ -32,8 +32,12 @@ MTLO1 011100 ..... 0000000000 00000 010011 @rs
# MMI2 # MMI2
PCPYLD 011100 ..... ..... ..... 01110 001001 @rs_rt_rd PCPYLD 011100 ..... ..... ..... 01110 001001 @rs_rt_rd
PAND 011100 ..... ..... ..... 10010 001001 @rs_rt_rd
PXOR 011100 ..... ..... ..... 10011 001001 @rs_rt_rd
# MMI3 # MMI3
PCPYUD 011100 ..... ..... ..... 01110 101001 @rs_rt_rd PCPYUD 011100 ..... ..... ..... 01110 101001 @rs_rt_rd
POR 011100 ..... ..... ..... 10010 101001 @rs_rt_rd
PNOR 011100 ..... ..... ..... 10011 101001 @rs_rt_rd
PCPYH 011100 00000 ..... ..... 11011 101001 @rt_rd PCPYH 011100 00000 ..... ..... 11011 101001 @rt_rd

54
target/mips/tcg/tx79_translate.c
View File

@ -2,6 +2,7 @@
* Toshiba TX79-specific instructions translation routines * Toshiba TX79-specific instructions translation routines
* *
* Copyright (c) 2018 Fredrik Noring * Copyright (c) 2018 Fredrik Noring
* Copyright (c) 2021 Philippe Mathieu-Daudé
* *
* SPDX-License-Identifier: GPL-2.0-or-later * SPDX-License-Identifier: GPL-2.0-or-later
*/ */
@ -114,6 +115,35 @@ static bool trans_MTLO1(DisasContext *ctx, arg_rtype *a)
* PSUBUW rd, rs, rt Parallel Subtract with Unsigned saturation Word * PSUBUW rd, rs, rt Parallel Subtract with Unsigned saturation Word
*/ */
static bool trans_parallel_arith(DisasContext *ctx, arg_rtype *a,
void (*gen_logic_i64)(TCGv_i64, TCGv_i64, TCGv_i64))
{
TCGv_i64 ax, bx;
if (a->rd == 0) {
/* nop */
return true;
}
ax = tcg_temp_new_i64();
bx = tcg_temp_new_i64();
/* Lower half */
gen_load_gpr(ax, a->rs);
gen_load_gpr(bx, a->rt);
gen_logic_i64(cpu_gpr[a->rd], ax, bx);
/* Upper half */
gen_load_gpr_hi(ax, a->rs);
gen_load_gpr_hi(bx, a->rt);
gen_logic_i64(cpu_gpr_hi[a->rd], ax, bx);
tcg_temp_free(bx);
tcg_temp_free(ax);
return true;
}
/* /*
* Min/Max (4 instructions) * Min/Max (4 instructions)
* ------------------------ * ------------------------
@ -139,6 +169,30 @@ static bool trans_MTLO1(DisasContext *ctx, arg_rtype *a)
* PNOR rd, rs, rt Parallel NOR * PNOR rd, rs, rt Parallel NOR
*/ */
/* Parallel And */
static bool trans_PAND(DisasContext *ctx, arg_rtype *a)
{
return trans_parallel_arith(ctx, a, tcg_gen_and_i64);
}
/* Parallel Or */
static bool trans_POR(DisasContext *ctx, arg_rtype *a)
{
return trans_parallel_arith(ctx, a, tcg_gen_or_i64);
}
/* Parallel Exclusive Or */
static bool trans_PXOR(DisasContext *ctx, arg_rtype *a)
{
return trans_parallel_arith(ctx, a, tcg_gen_xor_i64);
}
/* Parallel Not Or */
static bool trans_PNOR(DisasContext *ctx, arg_rtype *a)
{
return trans_parallel_arith(ctx, a, tcg_gen_nor_i64);
}
/* /*
* Shift (9 instructions) * Shift (9 instructions)
* ---------------------- * ----------------------