mirror of https://github.com/xemu-project/xemu.git
target-ppc: make cpu-qom.h not target specific
Make PowerPCCPU an opaque type within cpu-qom.h, and move all definitions of private methods, as well as all type definitions that require knowledge of the layout to cpu.h. Conversely, move all definitions needed to define a class to cpu-qom.h. This helps making files independent of NEED_CPU_H if they only need to pass around CPU pointers. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini
parent
c771dabf55
commit
2d34fe392c
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@ -38,6 +38,115 @@
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OBJECT_GET_CLASS(PowerPCCPUClass, (obj), TYPE_POWERPC_CPU)
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OBJECT_GET_CLASS(PowerPCCPUClass, (obj), TYPE_POWERPC_CPU)
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typedef struct PowerPCCPU PowerPCCPU;
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typedef struct PowerPCCPU PowerPCCPU;
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typedef struct CPUPPCState CPUPPCState;
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typedef struct ppc_tb_t ppc_tb_t;
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typedef struct ppc_dcr_t ppc_dcr_t;
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/*****************************************************************************/
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/* MMU model */
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typedef enum powerpc_mmu_t powerpc_mmu_t;
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enum powerpc_mmu_t {
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POWERPC_MMU_UNKNOWN = 0x00000000,
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/* Standard 32 bits PowerPC MMU */
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POWERPC_MMU_32B = 0x00000001,
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/* PowerPC 6xx MMU with software TLB */
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POWERPC_MMU_SOFT_6xx = 0x00000002,
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/* PowerPC 74xx MMU with software TLB */
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POWERPC_MMU_SOFT_74xx = 0x00000003,
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/* PowerPC 4xx MMU with software TLB */
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POWERPC_MMU_SOFT_4xx = 0x00000004,
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/* PowerPC 4xx MMU with software TLB and zones protections */
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POWERPC_MMU_SOFT_4xx_Z = 0x00000005,
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/* PowerPC MMU in real mode only */
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POWERPC_MMU_REAL = 0x00000006,
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/* Freescale MPC8xx MMU model */
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POWERPC_MMU_MPC8xx = 0x00000007,
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/* BookE MMU model */
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POWERPC_MMU_BOOKE = 0x00000008,
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/* BookE 2.06 MMU model */
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POWERPC_MMU_BOOKE206 = 0x00000009,
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/* PowerPC 601 MMU model (specific BATs format) */
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POWERPC_MMU_601 = 0x0000000A,
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#define POWERPC_MMU_64 0x00010000
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#define POWERPC_MMU_1TSEG 0x00020000
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#define POWERPC_MMU_AMR 0x00040000
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/* 64 bits PowerPC MMU */
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POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
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/* Architecture 2.03 and later (has LPCR) */
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POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002,
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/* Architecture 2.06 variant */
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POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
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| POWERPC_MMU_AMR | 0x00000003,
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/* Architecture 2.06 "degraded" (no 1T segments) */
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POWERPC_MMU_2_06a = POWERPC_MMU_64 | POWERPC_MMU_AMR
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| 0x00000003,
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/* Architecture 2.07 variant */
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POWERPC_MMU_2_07 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
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| POWERPC_MMU_AMR | 0x00000004,
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/* Architecture 2.07 "degraded" (no 1T segments) */
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POWERPC_MMU_2_07a = POWERPC_MMU_64 | POWERPC_MMU_AMR
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| 0x00000004,
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};
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/*****************************************************************************/
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/* Exception model */
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typedef enum powerpc_excp_t powerpc_excp_t;
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enum powerpc_excp_t {
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POWERPC_EXCP_UNKNOWN = 0,
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/* Standard PowerPC exception model */
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POWERPC_EXCP_STD,
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/* PowerPC 40x exception model */
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POWERPC_EXCP_40x,
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/* PowerPC 601 exception model */
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POWERPC_EXCP_601,
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/* PowerPC 602 exception model */
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POWERPC_EXCP_602,
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/* PowerPC 603 exception model */
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POWERPC_EXCP_603,
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/* PowerPC 603e exception model */
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POWERPC_EXCP_603E,
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/* PowerPC G2 exception model */
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POWERPC_EXCP_G2,
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/* PowerPC 604 exception model */
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POWERPC_EXCP_604,
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/* PowerPC 7x0 exception model */
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POWERPC_EXCP_7x0,
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/* PowerPC 7x5 exception model */
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POWERPC_EXCP_7x5,
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/* PowerPC 74xx exception model */
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POWERPC_EXCP_74xx,
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/* BookE exception model */
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POWERPC_EXCP_BOOKE,
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/* PowerPC 970 exception model */
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POWERPC_EXCP_970,
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/* POWER7 exception model */
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POWERPC_EXCP_POWER7,
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/* POWER8 exception model */
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POWERPC_EXCP_POWER8,
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};
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/*****************************************************************************/
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/* Input pins model */
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typedef enum powerpc_input_t powerpc_input_t;
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enum powerpc_input_t {
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PPC_FLAGS_INPUT_UNKNOWN = 0,
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/* PowerPC 6xx bus */
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PPC_FLAGS_INPUT_6xx,
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/* BookE bus */
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PPC_FLAGS_INPUT_BookE,
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/* PowerPC 405 bus */
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PPC_FLAGS_INPUT_405,
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/* PowerPC 970 bus */
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PPC_FLAGS_INPUT_970,
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/* PowerPC POWER7 bus */
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PPC_FLAGS_INPUT_POWER7,
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/* PowerPC 401 bus */
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PPC_FLAGS_INPUT_401,
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/* Freescale RCPU bus */
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PPC_FLAGS_INPUT_RCPU,
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};
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struct ppc_segment_page_sizes;
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/**
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/**
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* PowerPCCPUClass:
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* PowerPCCPUClass:
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@ -74,57 +183,7 @@ typedef struct PowerPCCPUClass {
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bool (*interrupts_big_endian)(PowerPCCPU *cpu);
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bool (*interrupts_big_endian)(PowerPCCPU *cpu);
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} PowerPCCPUClass;
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} PowerPCCPUClass;
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/**
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* PowerPCCPU:
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* @env: #CPUPPCState
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* @cpu_dt_id: CPU index used in the device tree. KVM uses this index too
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* @max_compat: Maximal supported logical PVR from the command line
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* @cpu_version: Current logical PVR, zero if in "raw" mode
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*
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* A PowerPC CPU.
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*/
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struct PowerPCCPU {
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/*< private >*/
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CPUState parent_obj;
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/*< public >*/
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CPUPPCState env;
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int cpu_dt_id;
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uint32_t max_compat;
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uint32_t cpu_version;
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};
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static inline PowerPCCPU *ppc_env_get_cpu(CPUPPCState *env)
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{
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return container_of(env, PowerPCCPU, env);
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}
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#define ENV_GET_CPU(e) CPU(ppc_env_get_cpu(e))
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#define ENV_OFFSET offsetof(PowerPCCPU, env)
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PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr);
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PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr);
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void ppc_cpu_do_interrupt(CPUState *cpu);
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bool ppc_cpu_exec_interrupt(CPUState *cpu, int int_req);
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void ppc_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
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int flags);
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void ppc_cpu_dump_statistics(CPUState *cpu, FILE *f,
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fprintf_function cpu_fprintf, int flags);
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int ppc_cpu_get_monitor_def(CPUState *cs, const char *name,
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uint64_t *pval);
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hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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int ppc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
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int ppc_cpu_gdb_read_register_apple(CPUState *cpu, uint8_t *buf, int reg);
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int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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int ppc_cpu_gdb_write_register_apple(CPUState *cpu, uint8_t *buf, int reg);
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int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
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int cpuid, void *opaque);
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#ifndef CONFIG_USER_ONLY
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#ifndef CONFIG_USER_ONLY
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void ppc_cpu_do_system_reset(CPUState *cs);
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extern const struct VMStateDescription vmstate_ppc_cpu;
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typedef struct PPCTimebase {
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typedef struct PPCTimebase {
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uint64_t guest_timebase;
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uint64_t guest_timebase;
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int64_t time_of_the_day_ns;
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int64_t time_of_the_day_ns;
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165
target-ppc/cpu.h
165
target-ppc/cpu.h
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@ -76,7 +76,7 @@
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#define CPUArchState struct CPUPPCState
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#define CPUArchState struct CPUPPCState
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#include "exec/cpu-defs.h"
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#include "exec/cpu-defs.h"
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#include "cpu-qom.h"
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#include "fpu/softfloat.h"
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#include "fpu/softfloat.h"
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#if defined (TARGET_PPC64)
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#if defined (TARGET_PPC64)
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@ -85,93 +85,6 @@
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#define PPC_ELF_MACHINE EM_PPC
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#define PPC_ELF_MACHINE EM_PPC
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#endif
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#endif
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/*****************************************************************************/
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/* MMU model */
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typedef enum powerpc_mmu_t powerpc_mmu_t;
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enum powerpc_mmu_t {
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POWERPC_MMU_UNKNOWN = 0x00000000,
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/* Standard 32 bits PowerPC MMU */
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POWERPC_MMU_32B = 0x00000001,
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/* PowerPC 6xx MMU with software TLB */
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POWERPC_MMU_SOFT_6xx = 0x00000002,
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/* PowerPC 74xx MMU with software TLB */
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POWERPC_MMU_SOFT_74xx = 0x00000003,
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/* PowerPC 4xx MMU with software TLB */
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POWERPC_MMU_SOFT_4xx = 0x00000004,
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/* PowerPC 4xx MMU with software TLB and zones protections */
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POWERPC_MMU_SOFT_4xx_Z = 0x00000005,
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/* PowerPC MMU in real mode only */
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POWERPC_MMU_REAL = 0x00000006,
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/* Freescale MPC8xx MMU model */
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POWERPC_MMU_MPC8xx = 0x00000007,
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/* BookE MMU model */
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POWERPC_MMU_BOOKE = 0x00000008,
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/* BookE 2.06 MMU model */
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POWERPC_MMU_BOOKE206 = 0x00000009,
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/* PowerPC 601 MMU model (specific BATs format) */
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POWERPC_MMU_601 = 0x0000000A,
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#if defined(TARGET_PPC64)
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#define POWERPC_MMU_64 0x00010000
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#define POWERPC_MMU_1TSEG 0x00020000
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#define POWERPC_MMU_AMR 0x00040000
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/* 64 bits PowerPC MMU */
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POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
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/* Architecture 2.03 and later (has LPCR) */
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POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002,
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/* Architecture 2.06 variant */
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POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
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| POWERPC_MMU_AMR | 0x00000003,
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/* Architecture 2.06 "degraded" (no 1T segments) */
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POWERPC_MMU_2_06a = POWERPC_MMU_64 | POWERPC_MMU_AMR
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| 0x00000003,
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/* Architecture 2.07 variant */
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POWERPC_MMU_2_07 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
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| POWERPC_MMU_AMR | 0x00000004,
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/* Architecture 2.07 "degraded" (no 1T segments) */
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POWERPC_MMU_2_07a = POWERPC_MMU_64 | POWERPC_MMU_AMR
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| 0x00000004,
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#endif /* defined(TARGET_PPC64) */
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};
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/*****************************************************************************/
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/* Exception model */
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typedef enum powerpc_excp_t powerpc_excp_t;
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enum powerpc_excp_t {
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POWERPC_EXCP_UNKNOWN = 0,
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/* Standard PowerPC exception model */
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POWERPC_EXCP_STD,
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/* PowerPC 40x exception model */
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POWERPC_EXCP_40x,
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/* PowerPC 601 exception model */
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POWERPC_EXCP_601,
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/* PowerPC 602 exception model */
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POWERPC_EXCP_602,
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/* PowerPC 603 exception model */
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POWERPC_EXCP_603,
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/* PowerPC 603e exception model */
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POWERPC_EXCP_603E,
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/* PowerPC G2 exception model */
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POWERPC_EXCP_G2,
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/* PowerPC 604 exception model */
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POWERPC_EXCP_604,
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/* PowerPC 7x0 exception model */
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POWERPC_EXCP_7x0,
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/* PowerPC 7x5 exception model */
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POWERPC_EXCP_7x5,
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/* PowerPC 74xx exception model */
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POWERPC_EXCP_74xx,
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/* BookE exception model */
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POWERPC_EXCP_BOOKE,
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#if defined(TARGET_PPC64)
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/* PowerPC 970 exception model */
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POWERPC_EXCP_970,
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/* POWER7 exception model */
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POWERPC_EXCP_POWER7,
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/* POWER8 exception model */
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POWERPC_EXCP_POWER8,
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#endif /* defined(TARGET_PPC64) */
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};
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/*****************************************************************************/
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/*****************************************************************************/
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/* Exception vectors definitions */
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/* Exception vectors definitions */
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enum {
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enum {
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@ -297,27 +210,6 @@ enum {
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POWERPC_EXCP_TRAP = 0x40,
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POWERPC_EXCP_TRAP = 0x40,
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};
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};
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/*****************************************************************************/
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/* Input pins model */
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typedef enum powerpc_input_t powerpc_input_t;
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enum powerpc_input_t {
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PPC_FLAGS_INPUT_UNKNOWN = 0,
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/* PowerPC 6xx bus */
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PPC_FLAGS_INPUT_6xx,
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/* BookE bus */
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PPC_FLAGS_INPUT_BookE,
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/* PowerPC 405 bus */
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PPC_FLAGS_INPUT_405,
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/* PowerPC 970 bus */
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PPC_FLAGS_INPUT_970,
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/* PowerPC POWER7 bus */
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PPC_FLAGS_INPUT_POWER7,
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/* PowerPC 401 bus */
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PPC_FLAGS_INPUT_401,
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/* Freescale RCPU bus */
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PPC_FLAGS_INPUT_RCPU,
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};
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#define PPC_INPUT(env) (env->bus_model)
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#define PPC_INPUT(env) (env->bus_model)
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/*****************************************************************************/
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/*****************************************************************************/
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@ -325,11 +217,8 @@ typedef struct opc_handler_t opc_handler_t;
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/*****************************************************************************/
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/*****************************************************************************/
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/* Types used to describe some PowerPC registers */
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/* Types used to describe some PowerPC registers */
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typedef struct CPUPPCState CPUPPCState;
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typedef struct DisasContext DisasContext;
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typedef struct DisasContext DisasContext;
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typedef struct ppc_tb_t ppc_tb_t;
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typedef struct ppc_spr_t ppc_spr_t;
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typedef struct ppc_spr_t ppc_spr_t;
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typedef struct ppc_dcr_t ppc_dcr_t;
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typedef union ppc_avr_t ppc_avr_t;
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typedef union ppc_avr_t ppc_avr_t;
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typedef union ppc_tlb_t ppc_tlb_t;
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typedef union ppc_tlb_t ppc_tlb_t;
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@ -1215,7 +1104,57 @@ do { \
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env->wdt_period[3] = (d_); \
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env->wdt_period[3] = (d_); \
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} while (0)
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} while (0)
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#include "cpu-qom.h"
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/**
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* PowerPCCPU:
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* @env: #CPUPPCState
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* @cpu_dt_id: CPU index used in the device tree. KVM uses this index too
|
||||||
|
* @max_compat: Maximal supported logical PVR from the command line
|
||||||
|
* @cpu_version: Current logical PVR, zero if in "raw" mode
|
||||||
|
*
|
||||||
|
* A PowerPC CPU.
|
||||||
|
*/
|
||||||
|
struct PowerPCCPU {
|
||||||
|
/*< private >*/
|
||||||
|
CPUState parent_obj;
|
||||||
|
/*< public >*/
|
||||||
|
|
||||||
|
CPUPPCState env;
|
||||||
|
int cpu_dt_id;
|
||||||
|
uint32_t max_compat;
|
||||||
|
uint32_t cpu_version;
|
||||||
|
};
|
||||||
|
|
||||||
|
static inline PowerPCCPU *ppc_env_get_cpu(CPUPPCState *env)
|
||||||
|
{
|
||||||
|
return container_of(env, PowerPCCPU, env);
|
||||||
|
}
|
||||||
|
|
||||||
|
#define ENV_GET_CPU(e) CPU(ppc_env_get_cpu(e))
|
||||||
|
|
||||||
|
#define ENV_OFFSET offsetof(PowerPCCPU, env)
|
||||||
|
|
||||||
|
PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr);
|
||||||
|
PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr);
|
||||||
|
|
||||||
|
void ppc_cpu_do_interrupt(CPUState *cpu);
|
||||||
|
bool ppc_cpu_exec_interrupt(CPUState *cpu, int int_req);
|
||||||
|
void ppc_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
|
||||||
|
int flags);
|
||||||
|
void ppc_cpu_dump_statistics(CPUState *cpu, FILE *f,
|
||||||
|
fprintf_function cpu_fprintf, int flags);
|
||||||
|
int ppc_cpu_get_monitor_def(CPUState *cs, const char *name,
|
||||||
|
uint64_t *pval);
|
||||||
|
hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
|
||||||
|
int ppc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
|
||||||
|
int ppc_cpu_gdb_read_register_apple(CPUState *cpu, uint8_t *buf, int reg);
|
||||||
|
int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
|
||||||
|
int ppc_cpu_gdb_write_register_apple(CPUState *cpu, uint8_t *buf, int reg);
|
||||||
|
int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
|
||||||
|
int cpuid, void *opaque);
|
||||||
|
#ifndef CONFIG_USER_ONLY
|
||||||
|
void ppc_cpu_do_system_reset(CPUState *cs);
|
||||||
|
extern const struct VMStateDescription vmstate_ppc_cpu;
|
||||||
|
#endif
|
||||||
|
|
||||||
/*****************************************************************************/
|
/*****************************************************************************/
|
||||||
PowerPCCPU *cpu_ppc_init(const char *cpu_model);
|
PowerPCCPU *cpu_ppc_init(const char *cpu_model);
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue